參數(shù)資料
型號(hào): XRT75L04IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LQFP-176
文件頁數(shù): 46/57頁
文件大小: 345K
代理商: XRT75L04IV
XRT75L04
44
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
0x1D
Receive Control
(read/write)
Reserved
DLOSDIS
_3
ALOSDIS
_3
RxClkINV
_3
LOSMUT_
3
RxMON_3 REQEN_3
0x1E
Block Control
(read/write)
Reserved
PRBSEN_
3
RLB_3
LLB_3
E3_3
STS1/
DS3_3
SR/DR_3
0x1F
Jitter Attenuator
(read/write)
Reserved
DFLCK_3 PNTRST_
3
JA1_3
JATx/
Rx_3
JA0_3
T
ABLE
21: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
0x01 (ch 0)
0x09 (ch 1)
0x11 (ch 2)
0x19 (ch 3)
R/W
Interrupt
Enable
(source
level)
D0
DMOIE_n
Set this bit to enable an interrupt when the no trans-
mission detected on channel output.
0
D1
RLOSIE_n Writng a “1” to this bit enables an interrupt when
Recieve Los of Signal is detected.
0
D2
RLOLIE_n
Writing a “1” to this bit enables an interrupt when
Receive Loss of Lock condition is detected
0
D3
FLIE_n
Writing a “1” to this bit enables the interrupt when
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
N
OTE
:
This bit field is ignored when the Jitter
Attenuator is disabled.
0
D4
PRBSERIE
_n
Set this bit to enable the interrupt when the PRBS
error is detected.
0
D5
PRBSERC
NTIE_n
Set this bit to enable the interrupt when the PRBS
error count register saturates.
0
D7-D6
Reserved
T
ABLE
20: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
3 R
EGISTERS
A
DDRESS
(H
EX
)
P
ARAMETER
N
AME
D
ATA
B
ITS
7
6
5
4
3
2
1
0
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