參數(shù)資料
型號: XRT75R03DIV-F
廠商: Exar Corporation
文件頁數(shù): 38/135頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標準包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-LQFP(14x20)
包裝: 托盤
XRT75R03D
128
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
REV. 1.0.4
"From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which
is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the
"high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities
that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3
data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame
synchronization within 50ms" after APS has been initiated."
The XRT75R03D was designed such that the DS3 signals that it receives from a SONET Mapper device and
processes will comply with the Category I Intrinsic Jitter requirements per Telcordia GR-253-CORE.
Reference 1 documents some APS Recovery Time testing, which was performed to verify that the Jitter
Attenuator blocks (within the XRT75R03D) device that permit it to comply with the Category I Intrinsic Jitter
Requirements (for DS3 Applications) per Telcordia GR-253-CORE, do not cause it to fail to comply with the
"APS Completion Time" requirements per Section 5.3.3.3 of Telcordia GR-253-CORE.
However, Table 3
presents a summary of some APS Recovery Time requirements that were documented within this test report.
Table 3,
NOTE: The APS Completion (or Recovery) time requirement is 50ms.
Configuring the XRT75R03D to be able to comply with the SONET APS Recovery Time Requirements of
50ms
Quite simply, the user can configure a given Jitter Attenuator block (associated with a given channel) to (1)
comply with the "APS Completion Time" requirements per Telcordia GR-253-CORE, and (2) also comply with
the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications) by making
sure that Bit 4 (SONET APS Recovery Time Disable Ch_n), within the Jitter Attenuator Control Register is set
to "0" as depicted below.
TABLE 33: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET
DS3 PPM OFFSET (PER W&G ANT-20SE)
MEASURED APS RECOVERY TIME (PER LOGIC ANALYZER)
-99 ppm
1.25ms
-40ppm
1.54ms
-30 ppm
1.34ms
-20 ppm
1.49ms
-10 ppm
1.30ms
0 ppm
1.89ms
+10 ppm
1.21ms
+20 ppm
1.64ms
+30 ppm
1.32ms
+40 ppm
1.25ms
+99 ppm
1.35ms
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