F
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XRT75VL00DIV
寤犲晢锛� Exar Corporation
鏂囦欢闋佹暩(sh霉)锛� 14/92闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC LIU E3/DS3/STS-1 1CH 52TQFP
妯�(bi膩o)婧栧寘瑁濓細 96
椤炲瀷锛� 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛�
椹�(q奴)鍕曞櫒/鎺ユ敹鍣ㄦ暩(sh霉)锛� 1/1
瑕�(gu墨)绋嬶細 DS3锛孍3锛孲TS-1
闆绘簮闆诲锛� 3.135 V ~ 3.465 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 52-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 52-TQFP锛�10x10锛�
鍖呰锛� 鎵樼洡
XRT75VL00D
16
REV. 1.0.4
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.0
TIMING CHARACTERISTICS
FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75VL00D (DUAL-RAIL DATA)
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle
E3
DS3
STS-1
30
50
34.368
44.736
51.84
70
%
MHz
tRTX
TxClk Rise Time (10% to 90%)
4
ns
tFTX
TxClk Fall Time (10% to 90%)
4
ns
tTSU
TPData/TNData to TxClk falling set up time
3
ns
tTHO
TPData/TNData to TxClk falling hold time
3
ns
tTDY
TTIP/TRing to TxClk rising propagation delay time
8
ns
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Transmit
Logic
Block
TxPOS
TxNEG
TxLineClk
TPData
TNData
TxClk
TPData or
TN Data
TTIP or
TRing
TxC lk
t
T SU
t
T H O
t
R T X
t
F TX
t
T D Y
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
XRT75VL00DIV-F 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
XRT75VL00DIVTR 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
XRT75VL00DIVTR-F 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
XRT75VL00ES 鍔熻兘鎻忚堪:鏅傞悩鍚堟垚鍣�/鎶栧嫊娓呴櫎鍣� 1CHT3/E3/STS1LIU+A 3.3V VOLTAGE DRIVE RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
XRT75VL00IV 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray