- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗1977 > XRT75VL00DIV (Exar Corporation)IC LIU E3/DS3/STS-1 1CH 52TQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | XRT75VL00DIV |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 90/92闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 96 |
| 椤�(l猫i)鍨嬶細 | 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛� |
| 椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� | 1/1 |
| 瑕�(gu墨)绋嬶細 | DS3锛孍3锛孲TS-1 |
| 闆绘簮闆诲锛� | 3.135 V ~ 3.465 V |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 52-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 52-TQFP锛�10x10锛� |
| 鍖呰锛� | 鎵樼洡(p谩n) |
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XRT75VL00D
85
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the LIU is operating in the Host Mode. If the
user is operating the LIU in the Hardware Mode, then the user will have NO ability to disable the "SONET APS
Recovery Time Mode" feature.
9.8.4
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end
Customer's site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our
SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their
end-customers that are evaluating and testing out their systems (in order to determine if they wish to move
forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out
these systems with a single piece of test equipment. This means that the end-customer would like to take a
single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic
(that this test equipment will generate) through many or (preferably all) channels within the system.
For
example, we have had request from our customers that (on a system that supports OC-192) our silicon be able
to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system.
After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain"
Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the LIU)
into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel of the LIU) to
operate in this mode by settings in the table below.
REFERENCES
1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH THE
XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
R/O
R/W
0
1
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS
Recovery
Time Disable
Ch_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/W
0
1
0
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
| XRT82D20IW-F | IC LIU E1 SGL 28SOJ |
| XRT82L24AIV-F | IC LIU E1 QAUD 100TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XRT75VL00DIV-F | 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊(d貌ng)娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel |
| XRT75VL00DIVTR | 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊(d貌ng)娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel |
| XRT75VL00DIVTR-F | 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊(d貌ng)娓呴櫎鍣� 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel |
| XRT75VL00ES | 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊(d貌ng)娓呴櫎鍣� 1CHT3/E3/STS1LIU+A 3.3V VOLTAGE DRIVE RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel |
| XRT75VL00IV | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
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