- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376462 > XRT8000ID (EXAR CORP) Clock Synchronizer/Adapter for Communications PDF資料下載
參數(shù)資料
| 型號： | XRT8000ID |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Synchronizer/Adapter for Communications |
| 中文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO18 |
| 封裝： | 0.300 INCH, SOIC-18 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 513K |
| 代理商： | XRT8000ID |
XRT8000
7
Rev. 1.11
SYSTEM DESCRIPTION
On power up the clock outputs of XRT8000
tri-stated. This means that no clocks will be seen at the
outputs and lock detect output will be low. After power up
the XRT8000 needs to be initialized. Therefore a serial
interface is provided to load the internal registers. These
registers will define the modes of operation, the output
frequencies and enabling the clock outputs.
will be
Master/Forward Mode of Operation
When
“Master/Forward”
“n x 2.048 MHz” or “n x 1.544 MHz” clock signal at the
FIN input (pin3); where “n” can range from 1 to 16. From
thisinput signal,the XRT8000devicewillinternallydivide
and synthesize the following signals.
At the CLK1 and/or CLK2 output pins:
D
k x 56 kHz
D
k x 64 kHz
D
(k x 56 kHz)/8
D
(k x 64 kHz)/8
where k can range from 1 to 32.
At the SYNC Output pin:
D
8kHz
The user selects and configures the XRT8000 device to
generate
these
clock
frequencies
appropriate values into the Command Registers (CR1,
CR2, CR3, CR4 and CR5), via the Microprocessor Serial
Interface.
the
XRT8000
device
it
is
operating
receive
in
the
an
Mode,
will
either
by
writing
the
Reverse Mode of Operation
When the XRT8000 device is operating in the “Reverse”
Mode,itwillreceiveeithera56 kHzor64 kHzclocksignal
at the FIN input. From this input signal, the XRT8000
device will synthesize any of the following clock signal
frequencies.
At the CLK1 and/or CLK2 output pins:
D
1.544 MHz
D
2.048 MHz
D
1.544 MHz/8 = 193 kHz
D
2.048 MHz/8 = 256 kHz
At the SYNC output pin:
D
8 kHz
The user can configure the XRT8000 device to generate
these clock frequencies by writing the appropriate values
into the Command Registers (CR1, CR2, CR3, CR4 and
CR5), via the Microprocessor Serial Interface.
Note:
in the REVERSE mode the contents of CR3 and
CR4 has to be all one’s.
Slave (Forward, Reverse) Mode of Operation
To activate the slave modes of operations the input MSB
must be tied low. In these modes an 8kHz signal must be
applied to the FIN input in order to obtain output
frequenciesatT1orE1rates.Theoutputfrequenciescan
be selected via the serial interface in a similar fashion as
described in the master forward and reverse modes.
The Lock Detect Output Pin
If both PLL’s are enabled and in locked state then
LOCKDET will be active. If one PLL loses lock then
LOCKDET will be false. If only one PLL is enabled then
only the active PLL will control the state of LOCKDET.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設(shè)備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
| XRT8001IP | WAN Clock for T1 and E1 Systems |
| XRT8010 | 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T8000ID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Miscellaneous Clock Generator |
| XRT8000ID-F | 功能描述:時鐘合成器/抖動清除器 3.3V-5V 0.05UI temp -45 to 85C RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT8000IDTR-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8000IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000IP-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。