DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 8" />
參數(shù)資料
型號: XRT8000IDTR-F
廠商: Exar Corporation
文件頁數(shù): 19/24頁
文件大小: 0K
描述: IC WAN CLOCK E1/E1 DUAL 18SOIC
產(chǎn)品變化通告: Packaging Change 15/Jul/2010
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/頻率發(fā)生器,同步器,多路復(fù)用器
PLL:
主要目的: 電信
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 2.048MHz
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 帶卷 (TR)
XRT8000
4
Rev. 1.11
DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 85_C
Test Conditions: TA = 25_C, VCC = 5.0V ± 5% Unless Otherwise Specified
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VIL
Input low level
0.8
V
VIH
Input high level
2.0
V
VOL
Output low level (CLK1,CLK2)
0.4
V
IOL = -6.0 mA
VOH
Output high level (CLK1,CLK2)
2.4
V
IOH = 6.0 mA
VOL
Output low level (LOCKDET,SYNC)
0.4
V
IOL = -3.0 mA
VOH
Output high level (LOCKDET,SYNC)
2.4
V
IOH = 3.0 mA
IIL
Input low current (CSB,MSB)
-150
mA
IIH
Input high current (CSB,MSB)
10
mA
VIN = VCC
IIL
Input low current (except CSB,MSB)
-10
mA
IIH
Input high current (except CSB,MSB)
10
mA
VIN = VCC
ICC
Operating current
20
35
mA
No load. Clock = 2.1 MHz
RIN
Input pull-up resistance (CSB,MSB)
50
100
150
KW
AC ELECTRICAL CHARACTERISTICS (See Figure 3)
Symbol
Parameter
Spec.3
Min
Typ
Max
Unit
Conditions
T1
Input frequency
0.008
32.7
MHz
T2
Minimum input signal high to
low duration
12
ns
T3
Output frequency
1.2
2.1
KHz
T61
Duty cycle CLK1, CLK2
47.5
50
52.5
%
VCC/2 switch point. 30pF
load.
T74
Jitter added 8KHz-40KHz
0.025
0.007
0.02
UI
Output =1.544MHz
T74
Jitter added 10Hz-40KHz
0.025
0.022
UI
Output =1.544MHz
T74
Broad Band-jitter
0.05
0.03
0.05
UI
Output =1.544MHz
T74
Jitter added 20Hz-100KHz
1.5
0.05
0.07
UI
Output =2.048MHz
T74
Jitter added 18kHz-100KHz
0.2
0.01
0.03
UI
Output =2.048MHz
T8
Capture time
40
ms
T9
Clock output rise time
10
ns
30pF load. Measured at
20/80 %
T10
Clock output fall time
10
ns
30pF load. Measured at
20/80 %
T112
Duty cycle SYNC
40
60
%
VCC/2 switch point
(in master forward mode).
30pF load.
T14
Delay time between the rising
edge of SYNC and the rising
edge of CLK1 or CLK2
T-20
T
T+20
ns
See table 12 for values of T
Notes:
1 T6 = (
)
T
4
5
+
2 T11 = (
)
T
12
13
+
3 Specifications from AT&T Publication 62411 and ITU-T Recommendations G-823 (for 1.544MHz and 2.048MHz, respectively).
4 T7 is guaranteed by characterization, not tested.
Specifications are subject to change without notice.
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