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參數(shù)資料
| 型號： | XRT8000IDTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC WAN CLOCK E1/E1 DUAL 18SOIC |
| 產品變化通告： | Packaging Change 15/Jul/2010 |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器，同步器，多路復用器 |
| PLL： | 無 |
| 主要目的： | 電信 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.048MHz |
| 電源電壓： | 3.135 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 18-SOIC |
| 包裝： | 帶卷 (TR) |
XRT8000
15
Rev. 1.11
Using the Serial Interface
The following instructions, for using the serial interface,
are best understood by referring to the diagram in
Figure 4.
In order to use the serial interface the user must first
provide a clock signal to the SCLK input pin. Afterwards,
the user will initiates a “Read” or “Write” operation by
asserting the active low Chip Select Input pin (CSB). It is
important to note that the user assert CSB low coincident
with the falling edge of SCLK.
Once the CSB input has been asserted the type of
operation and the target register address must be
provided by the user. The user will provide this
information to the serial interface by writing four serial bits
of data to the SDI input. Note: Each of these bits will be
“clocked” into the SDI input, on the rising edge of SCLK.
These four bits are identified and described below.
Bit 1: The R/W (Read/Write) Bit
This bit will be clocked into the SDI input, on the first rising
edge of SCLK (after CSB has been asserted). This bit
indicates whether the current operation is a read or a write
operation. A “1” in this bit will cause a “Read” operation;
whereas a “0” in this bit will cause a “Write” operation.
Bits 2 through 4: The three (3) bit address value (A0,
A1, A2)
These next three rising edges of the SCLK signal will
clock in the 3-bit address value for this particular read (or
write) operation. This address selects the command
register within XRT8000 device that the user will either be
reading data from, or writing data to. The user must
supply the address bits to the SDI input pin, in ascending
order with the LSB first. (A3 to A5 must be low A6 is a
“don’t care”).
Once the “Read/Write” and Address bits have been
written, the subsequent action depends upon whether the
current operation is a “Read” or “Write” operation.
Read Operation
Once the last address bit (A2) has been clocked into the
SDI input, the read operation will proceed through an idle
period, lasting four SCLK periods. On the falling edge of
SCLK Cycle “8” (See Figure 4) the serial output signal
(SDO) becomes active. At this point the user can begin
reading the data contents of the addressed command
register (at Address A2, A1, A0) via the SDO pin. The
SDO pin will output this five bit data word (D0 through D4)
in ascending order, with the LSB first, on the rising edges
of the SCLK pin.
Write Operation
Once the last address bit (A2) has been clocked into the
SDI input, the write operation will proceed through an idle
period, lasting four SCLK periods. Prior to the rising edge
of SCLK Cycle #9 (See Figure 4) the user must begin to
apply the eight-bit data word, that he/she wishes to write
to the serial input interface onto the SDI input pin. The
microprocessor serial interface will catch the value on the
SDI pin on the rising edge of the SCLK. The user must
apply this word (D0 through D7), serially, in ascending
order with the LSB first.
Simplified Interface Option
The user can simplify the design of the circuitry
connecting to the serial interface by tying both the SDO
and SDI pins together, and reading data from and/or
writing data to this “combined” signal. This simplification
is possible because only one of these signals are active at
any given time. The inactive signal will be tri-stated.
Notes:
1. Prior to reading data from (or writing data to) the Serial Inter-
face, the user is not required to provide a clock signal at the
SCLK. However, shortly before performing any read or write
operations with the Serial Interface, the user must supply the
clock signal to the SCLK input pin.
2. Each Read or Write operation, with the Serial Interface, will
require 16 SCLK periods, as depicted in Figure 4.
3. Upon completion of a Read or Write cycle, the user must ne-
gate CSB for at least 250ns (see timing parameter T29 in the
AC Characteristics), before asserting it again for the next
Read or Write operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT8000IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000IP-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001 | 制造商:EXAR 制造商全稱:EXAR 功能描述:WAN Clock for T1 and E1 Systems |
| XRT8001ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001ID | 制造商:Exar Corporation 功能描述:WAN Clock 18-Pin SOIC W |
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