參數(shù)資料
型號(hào)： AD9524BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/56頁(yè)
文件大小： 0K
描述： IC INTEGER-N CLCK GEN 48LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配）
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 標(biāo)準(zhǔn)包裝
配用： AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
其它名稱(chēng)： AD9524BCPZ-REEL7DKR
Jitter Cleaner and Clock Generator with
6 Differential or 13 LVCMOS Outputs
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2010–2014 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±150 ps
6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
6 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of period of VCO
output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: 160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and IC-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate of 300 kHz to 75 MHz
Redundant reference inputs
Auto and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate of up to 250 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
PLL1
REFA,
REFA
OUT0,
OUT0
OUT1,
OUT1
OUT4,
OUT4
OUT5,
OUT5
OSC
REFB,
REFB
REF_TEST
SCLK/SCL
SDIO/SDA
SDO
ZD_IN, ZD_IN
CONTROL
INTERFACE
(SPI AND I2C)
EEPROM
PLL2
ZERO
DELAY
AD9524
6-CLOCK
DISTRIBUTION
09081-
001
Figure 1.
GENERAL DESCRIPTION
The AD9524 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to
4.0 GHz.
The AD9524 is defined to support the clock requirements for
long term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive low phase noise require-
ments necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates six low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to one-half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user defined register settings for power-up and
chip reset.
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AD9525/PCBZ-VCO 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9525BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9525BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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