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參數(shù)資料
| 型號： | XRT82D20 |
| 廠商： | Exar Corporation |
| 英文描述： | Single Channel E1 Line Interface Unit(單通道E1線接口單元) |
| 中文描述： | 單通道E1線路接口單元（單通道素E1線接口單元） |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 236K |
| 代理商： | XRT82D20 |
XRT82D20
SINGLE CHANNEL E1 LINE INTERFACE UNIT
á
REV. 1.0.6
4
12
ATM
I
Alarm Test Mode (Active-Low):
Connect this pin to ground to force ClkLOS, RLOS = 0 and LCV = 1 for
testing without affecting data transmission. (internal pull-up)
13
RAOS
I
Receive All Ones:
With this pin tied to High, an all “1’s” signal is inserted to the receiver out-
put at RPOS and RNEG/RData using MCLK as timing reference. This
control has priority over Digital Loop-back if both are enabled. (internal
pull-down).
14
TAOS
I
Transmit All Ones:
With this pin tied High, an AMI encoded all “1’s” signal is sent to the
transmit output using MCLK as timing reference. This control has priority
over Remote Loop-back if both are enabled. (internal pull-down).
15
MClk
I
Master Clock Input:
This signal is an independent 2.048 MHz clock with accuracy better than
+ 50 ppM and duty cycle within 40% to 60%. The function of MClk is to
provide timing source for the PLL clock recovery circuit, reference clock
to insert all “1’s” data in the transmit as well as receive paths. This signal
must be available for the device to operate.
16
JATx/Rx
(DR/SR)
I
Jitter Attenuator Path Select.
With the jitter attenuator enabled, (pin 18 =”1”), tie this pin “High” to
select the jitter attenuator in the transmit path and tie it “Low” to select in
the receive path. Data input/output format is then controlled automati-
cally by the status of the TNEG input. If TNEG data is present the device
operates in Dual-rail data mode.
Dual-Rail/Single-Rail Select:
With the jitter attenuator disabled, (pin 18 =”0”), tie this pin “High” to
select Dual-Rail data format and tie it “Low” to select Single-Rail data for-
mat. (internal pull-down)
17
DIGI
I
Digital Interface:
With this pin tied Low, input data at TPOS/TData and TNEG/CODE is
active-high and will be sampled by TClk on the falling edge, while active-
high RPOS/RData and RNEG output data are updated on the falling
edge of RClk. See Figure 3 and 4 for details.
With his pin tied high and in Dual-rail mode, transmit input accepts
active-low TPOS/TData and TNEG/CODE data and will be sampled by
TClk on the falling edge, while RPOS/RData and RNEG/LCV are active-
low, data is updated on the rising edge of RClk. (internal pull-down).
18
JAEN
I
Jitter Attenuator Enable (active high):
Connect this pin high to enable the jitter attenuation function.Jitter Atten-
uator Path select is determined by the pin 16 setting. (internal pull-down)
19
TGND
-
Transmitter Supply Ground
20
TRing
O
Transmitter Ring Output.
Negative bipolar data output to the line.
21
TVDD
-
Transmit Positive Supply.
5.0 V + 5% or 3.3 V + 5%
22
TTIP
O
Transmitter TIP Output.
Positive bipolar data output to the line.
23
TxLEV
I
Transmit Level.
Tie this pin high for 120
twisted pair cable operation and tie it low for 75
coaxial cable operation (internal pull-down). This pin is only active for
5.0V operation.
P
IN
#
S
YMBOL
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D
ESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82D20_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CH E1 LIU RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT82D20IW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single Ch E1 LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT82D20IW-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT82D20IW-F | 制造商:Exar Corporation 功能描述:T1/E1 LIU IC |
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