參數(shù)資料
型號: XRT86VL32
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 120/174頁
文件大小: 903K
代理商: XRT86VL32
XRT86VL32
115
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
100: D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
1 (DLIER1) H
EX
A
DDRESS
: 0
X
nB07
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
-
-
Reserved
6
TxSOT ENB
R/W
0
Transmit HDLC1 Controller Start of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC1
Controller Start of Transmission (TxSOT) “Interrupt within the
XRT86VL32 device. Once this interrupt is enabled, the Transmit
HDLC1 Controller will generate an interrupt when it has started to
transmit a data link message.
0 = Disables the Transmit HDLC1 Controller Start of Transmission
(TxSOT) interrupt.
1 = Enables the Transmit HDLC1 Controller Start of Transmission
(TxSOT) interrupt.
5
RxSOT ENB
R/W
0
Receive HDLC1 Controller Start of Reception (RxSOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC1
Controller Start of Reception (RxSOT) “Interrupt within the
XRT86VL32 device. Once this interrupt is enabled, the Receive
HDLC1 Controller will generate an interrupt when it has started to
receive a data link message.
0 = Disables the Receive HDLC1 Controller Start of Reception
(RxSOT) interrupt.
1 = Enables the Receive HDLC1 Controller Start of Reception
(RxSOT) interrupt.
4
TxEOT ENB
R/W
0
Transmit HDLC1 Controller End of Transmission (TxEOT) Inter-
rupt Enable
This bit enables or disables the “Transmit HDLC1
Controller End of Transmission (TxEOT) “Interrupt within the
XRT86VL32 device. Once this interrupt is enabled, the Transmit
HDLC1 Controller will generate an interrupt when it has finished
transmitting a data link message.
0 = Disables the Transmit HDLC1 Controller End of Transmission
(TxEOT) interrupt.
1 = Enables the Transmit HDLC1 Controller End of Transmission
(TxEOT) interrupt.
3
RxEOT ENB
R/W
0
Receive HDLC1 Controller End of Reception (RxEOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC1
Controller End of Reception (RxEOT) “Interrupt within the
XRT86VL32 device. Once this interrupt is enabled, the Receive
HDLC1 Controller will generate an interrupt when it has finished
receiving a complete data link message.
0 = Disables the Receive HDLC1 Controller End of Reception
(RxEOT) interrupt.
1 = Enables the Receive HDLC1 Controller End of Reception
(RxEOT) interrupt.
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