參數(shù)資料
型號： XRT86VL32
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 50/174頁
文件大小： 903K
代理商： XRT86VL32
XRT86VL32
45
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
27: T
RANSMIT
I
NTERFACE
C
ONTROL
R
EGISTER
(TICR) H
EX
A
DDRESS
:0
X
n120
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
TxSyncFrD
R/W
0
Transmit Synchronous fraction data interface
This bit selects whether TxCHCLK or TxSERCLK will be used for frac-
tional data input if the transmit fractional interface is enabled. If TxSER-
CLK is selected to clock in fractional data input, TxCHCLK will be used
as an enable signal
0 = Fractional data Is clocked into the chip using TxChCLK if the trans-
mit fractional data interface is enabled.
1 = Fractional data is clocked into the chip using TxSerClk if the trans-
mit fractional data interface is enabled. TxChClk is used as fractional
data enable.
N
OTE
:
The Time Slot Identifier Pins (TxChn[4:0]) still indicates the time
slot number if the transmit fractional data interface is not
enabled. Fractional Interface can be enabled by setting
TxFr2048 to 1
6
Reserved
-
-
Reserved
5
TxPLClkEnb
R/W
0
Transmit payload clock enable
This bit configures the E1 framer to output a regular clock or a payload
clock on the transmit serial clock (TxSERCLK) pin when TxSERCLK is
configured to be an output.
0 = Configures the framer to output a 2.048MHz clock on the TxSER-
CLK pin when TxSERCLK is configured as an output.
1 = Configures the framer to output a 2.048MHz clock on the TxSER-
CLK pin when transmitting payload bits. There will be gaps on the
TxSERCLK output pin when transmitting overhead bits.
4
TxFr2048
R/W
0
Transmit Fractional/Signaling Interface Enabled
This bit is used to enable or disable the transmit fractional data inter-
face, signaling input, as well as the 32MHz transmit clock and the trans-
mit overhead Signal output. This bit only functions when the device is
configured in non-high speed or multiplexed modes of operations.
If the device is configured in base rate:
0 = Configures the 5 time slot identifier pins (TxChn[4:0]) to output the
channel number as usual.
1 = Configures the 5 time slot identifier pins (TxChn[4:0]) into the follow-
ing different functions:
TxChn[0] becomes the Transmit Serial SIgnaling pin (TxSIG_n) for sig-
naling inputs. Signaling data can now be input from the TxSIG pin if
configured appropriately.
TxChn[1] becomes the Transmit Fractional Data Input pin (TxFrTD_n)
for fractional data input. Fractional data can now be input from the
TxFrTD pin if configured appropriately.
TxChn[2] becomes the 32 MHz transmit clock output
TxChn[3] becomes the Transmit Overhead Signal which pulses high on
the first bit of each multi-frame.
N
OTE
:
This bit has no function in the high speed or multiplexed modes
of operation. In high-speed or multiplexed modes, TxCHN[0]
functions as TxSIGn for signaling input.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL32_07 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL32_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_1 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_2 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL32ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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