參數(shù)資料
型號： XRT86VL32
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 67/174頁
文件大?。?/td> 903K
代理商： XRT86VL32
XRT86VL32
62
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
43: T
RANSMIT
Sa A
UTO
C
ONTROL
R
EGISTER
2 (TSACR2) H
EX
A
DDRESS
: 0
XN
132
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
AIS_1_ENB
R/W
0
AIS reception
This bit enables the automatic Sa-bit transmission upon detecting
AIS condition.
Upon detecting the AIS condition, E1 framer will transmit the Alarm
bit (A bit) as ‘1’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’.
See
Table 44
for the transmit Sa5, Sa6, and A bit pattern upon
detecting AIS condition.
6
AIS_2_ENB
R/W
0
AIS reception
This bit enables the automatic Sa-bit transmission upon detecting
AIS condition.
Upon detecting the AIS condition, E1 framer will transmit the Alarm
bit (A bit) as ‘0’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’.
See
Table 44
for the transmit Sa5, Sa6, and A bit pattern upon
detecting AIS condition.
5
Reserved
-
-
Reserved
4
Reserved
-
-
Reserved
3
CRCREP_ENB[1]
R/W
0
CRC report
These two bits enable the automatic Sa-bit transmission upon
detecting Far End Block Error (i.e. received E bit = 0).
Upon detecting the Far End Block Error (FEBE) condition, E1 framer
will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as
‘0000’, and E bit as ‘0’ pattern if these two bits are set to ‘01’.
If these two bits are set to ‘10’, E1 framer will transmit the Alarm bit
(A bit) as ‘0’, Sa5 bit as ‘0’, Sa6 bit as ‘0000’, and E bit as ‘0’ pattern
upon detecting the Far End Block Error (FEBE).
If these two bits are set to ‘11’, E1 framer will transmit the Alarm bit
(A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0001’, and E bit as ‘1’ pattern
upon detecting the Far End Block Error (FEBE).
See
Table 44
for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting FEBE condition.
2
CRCREP_ENB[0]
R/W
0
1
CRCDET_ENB
R/W
0
CRC detection
This bit enables the automatic Sa-bit transmission upon detecting
CRC-4 error condition.
Upon detecting CRC-4 error condition, E1 framer will transmit the
Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0010’, and E bit as
‘1’ pattern.
See
Table 44
for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting CRC-4 error condition.
0
CRCREC AND
DET_ENB
R/W
0
CRC report and detect
This bit enables automatic Sa-bit transmission upon detecting both
Far End Block Error (FEBE) and CRC-4 error conditions.
Upon detecting both Far End Block Error (FEBE) and CRC-4 error
condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit
as ‘1’, Sa6 bit as ‘0011’, and E bit as ‘1’ pattern.
See
Table 44
for the transmit Sa5, Sa6, E, and A bit pattern upon
detecting both FEBE and CRC-4 error conditions.
相關(guān)PDF資料
PDF描述
XRT86VL32_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL32IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL32_07 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL32_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_1 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_2 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL32ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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