參數(shù)資料
型號: XRT91L30IQ
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PQFP64
封裝: 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-64
文件頁數(shù): 28/39頁
文件大小: 440K
代理商: XRT91L30IQ
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.1
26
Table 15 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
CDR or an external recovered clock in loop timing applications is shown in Figure 16.
T
ABLE
15: L
OOP
T
IMING
AND
C
LOCK
R
ECOVERY
CONFIGURATIONS
CDRDIS
LOOPTIME
T
RANSMIT
C
LOCK
S
OURCE
R
ECEIVE
C
LOCK
S
OURCE
0
0
Clock Multiplier Unit
CDR Enabled.
Clock and Data recovery by internal CDR
0
1
Internal CDR
CDR Enabled.
Clock and Data recovery by internal CDR
1
0
Clock Multiplier Unit
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
1
1
External CDR thru XRXCLKIP/N
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
F
IGURE
16. L
OOP
T
IMING
M
ODE
U
SING
I
NTERNAL
CDR
OR
AN
E
XTERNAL
R
ECOVERED
C
LOCK
RXIP
RXIN
M
CDR
MUX
M
REFCLKP
REFCLKN
TTLREFCLK
CDRDIS
Div by 8
Clk
Data
~
~
XRT91L30
LOOPTIME
XRXCLKIP
XRXCLKIN
DATA
PISO
to Retimer
SIPO
Retimer
TXOP
TXON
CLK
8
RXDO[7:0]
RXPCLKO
DATA
CLK
TXPCLK_IO
PIO_CTRL
ENB
ENB
M
0
1
Div by
8
8
TXDI[7:0]
622.08/
155.52MHz
CMU
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