參數(shù)資料
型號: XRT91L32IQ
廠商: Exar Corporation
文件頁數(shù): 14/37頁
文件大小: 0K
描述: IC TXRX SONET/SDH 8BIT 100QFP
產(chǎn)品變化通告: XRT91L32IQ(TR) Obsolescence 12/Oct/2010
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
包裝: 托盤
xr
XRT91L32
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
19
2.10
Receive Parallel Data Output Timing
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and
hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows the PECL and TTL output timing
specifications.
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING
TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)
TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tRXCLK
Receive high-speed serial clock period
1.608
ns
tRXPCLKO
Receive parallel data output byte clock period
12.86
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
4
ns
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
12.86
ns
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tRXCLK
Receive high-speed serial clock period
6.43
ns
tRXPCLKO
Receive parallel data output byte clock period
51.44
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
22
ns
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
51.44
ns
tRXCLK
RXPCLKO
RXDO[7:0]
RXIP
RXIN
FRAMEPULSE
tRXDO_VALID
tRXPCLKO
A1
A2
tPULSE_WID
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