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參數(shù)資料
| 型號： | XRT91L32IQTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/37頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 8BIT 100QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-QFP（14x20） |
| 包裝： | 帶卷 (TR) |
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XRT91L32
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.0
TRANSMIT SECTION
The transmit section of the XRT91L32 accepts 8-bit parallel data and converts it to serial Differential LVPECL
data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL
interface, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Low Voltage Positive-referenced Emitter-
Coupled Logic (LVPECL) differential line driver, and Loop Timing modes. The LVPECL serial data output rate is
622.08 Mbps for STS-12/STM-4 applications and 155.52 Mbps for STS-3/STM-1 applications. The high
frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In
order to synchronize the data transfer process, the synthesized 622.08 MHz for STS-12/STM-4 or 155.52 MHz
STS-3/STM-1 serial clock output is divided by eight and the 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/
STM-1) clock respectively is presented to the framer/mapper device to be used as its timing source.
3.1
Transmit Parallel Input Interface
The parallel data from an framer/mapper device is presented to the XRT91L32 through an 8-bit Single-Ended
LVTTL parallel bus interface TXDI[7:0]. To directly interface to the XRT91L32, the SONET Framer/ASIC must
be synchronized to the same timing source TXPCLK_IO in presenting data on the parallel bus interface. The
data must meet setup and hold times with respect to TXPCLK_IO. This clock output source is used to
synchronize the SONET Framer/ASIC to the XRT91L32. The framer/mapper device should use TXPCLK_IO
as its timing source so that parallel data is phase aligned with the serial transmit data. The data is latched into
a parallel input register on the rising edge of TXPCLK_IO. TXPCLK_IO is derived from a divide-by-8 of the high
speed synthesized clock resulting in a 77.76/ 19.44 MHz Single-Ended LVTTL clock output source to be used
by the framer/mapper device for parallel bus synchronization. A simplified block diagram of the transmit
parallel bus clock output system interface is shown in Figure 11.
FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
SONET Framer/ASIC
REFCLKP
TXPCLK_IO
TTLREFCLK
TXDI[7:0]
8
CMUREFSEL
REFCLKN
XRT91L32
STS-12/STM-4
or
STS-3/STM-1
Transceiver
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L33 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT |
| XRT91L33AIG-F | 制造商:Exar Corporation 功能描述:CDR 155.52Mbps/622.08Mbps SONET/SDH 20-Pin TSSOP |
| XRT91L33ES | 功能描述:界面開發(fā)工具 Eval System for XRT91L33 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XRT91L33IG | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT |
| XRT91L33IG-F | 功能描述:時鐘合成器/抖動清除器 Recovery Unit RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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