參數資料
| 型號： | XRT91L32IQTR-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 36/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH 8BIT 100QFP |
| 標準包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-QFP（14x20） |
| 包裝： | 帶卷 (TR) |
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XRT91L32
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
6
ALOOP
LVTTL
I
3
Analog Local Loopback
This loopback feature serializes the 8-bit parallel transmit data
input and presents the data to the transmit serial output and in
addition it also internally routes the serialized data back to the
Clock and Data Recovery block for serial to parallel conversion.
The received serial data input is ignored.
"Low" = Disabled
"High" = Analog Local Loopback Mode Enabled
DLOOP
LVTTL
I
100
DLOOP Local Loopback
This digital loopback mode interconnects the 8-bit parallel
transmit data input and TXCLK to the 8-bit parallel receive data
output and receive RXCLK respectively while maintaining the
transmit serial data output. If digital loopback is enabled, the
receive serial data input is ignored.
"Low" = Disabled
"High" = Digital Local Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature in normal
operation.
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXDI0
TXDI1
TXDI2
TXDI3
TXDI4
TXDI5
TXDI6
TXDI7
LVTTL
I
95
94
92
91
89
88
86
85
Transmit Parallel Data Input
Transmit Parallel Clock Output Operation
The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
8-bit parallel transmit data should be applied to the transmit
parallel bus and simultaneously referenced to the rising edge of
the TXPCLK_IO clock output. The 8-bit parallel interface is mul-
tiplexed into the transmit serial output interface with the MSB
first (TXDI[7:0]).
Alternate Transmit Parallel Clock Input Operation
When operating is this mode, TXPCLK_IO is no longer a paral-
lel clock output reference but reverses direction and serves as
the parallel transmit clock input reference for the PISO (Parallel
Input to Serial Output) block. The 77.76 Mbps (STS-12/STM-4)
/ 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should
be applied to the transmit parallel bus and simultaneously refer-
enced to the rising edge of the TXPCLK_IO clock input.
TXOP
TXON
LVPECL Diff
O
10
11
Transmit Serial Data Output
The transmit serial data stream is generated by multiplexing the
8-bit parallel transmit data input into a 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 serial data stream.
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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相關代理商/技術參數 |
參數描述 |
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| XRT91L33IG | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT |
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