參數(shù)資料
型號(hào): XTR108EA
英文描述: 4-20mA, TWO-WIRE TRANSMITTER Smart Programmable with Signal Conditioning
中文描述: 的4 - 20mA,兩線制變送器可編程智能與信號(hào)調(diào)理
文件頁(yè)數(shù): 13/27頁(yè)
文件大?。?/td> 497K
代理商: XTR108EA
XTR108
SBOS187B
13
www.ti.com
The uncommitted amplifier can be used for a variety of
purposes, such as voltage sensor excitation, buffering the
REF
OUT
pin, four-wire RTD connection, or sensing the
bridge voltage for temperature compensation.
POWER-GOOD/POWER-ON RESET
In case of a supply brownout condition or short interruption,
the XTR108 power-good detection circuit will initiate a chip
reset that will cause all registers to be reset to 0’s and a cycle
of EEPROM read to begin. The circuit generates a reset if
V
S
droops below 1.5V and then recovers up to the normal
level.
USING THE XTR108 IN VOLTAGE OUTPUT MODE
The XTR108 can be used not only in 4-20mA current loops,
but also as a low-power, single-supply, “smart” sensor-condi-
tioning chip with voltage output. In this mode, the pin I
RET
must be grounded. The sub-regulator with an external MOSFET
may or may not be used. If the circuit is powered externally,
the supply voltage must be in the range of 5V to
±
0.5V.
CONTROL REGISTERS
Table V shows the registers that control the analog functions
of the XTR108.
DESCRIPTION OF CONTROL REGISTERS
Address = 0: Control Register 1
If the RST bit is set to ‘1’ in a write operation, all the
registers in the XTR108 will be returned to their power-on
reset condition. The RST bit will always read as a ‘0’. CSE,
the checksum error bit, is read only and will be set to ‘1’ if
a checksum error has been detected. This bit is cleared by a
reset operation or by detection of a valid checksum. The
remaining bits are reserved and must be set to ‘0’.
Address = 3: Fault Status Register
This register is a read-only register. If the input voltage to
the PGA exceeds the linear range of operation, the XTR108
will indicate this error condition (typically caused by a
sensor fault) by setting the under-scale or over-scale error
level depending on the state of the Alarm Configuration
Register (Address = 7). Information on the nature of the fault
may be read in digital form from this register, as shown in
Table VI. The remaining bits will be set to ‘0’.
Address = 4: Control Register 2
If the RBD bit is set to ‘1’, the automatic read-back from the
EEPROM will be disabled after a valid checksum byte is
received in Register 15. This bit is read from the EEPROM
during a read-back by the XTR108 and allows the user to
program the XTR108 to read the EEPROM data once
(instead of continuously), and then disables the automatic
read-back function. The XTR108 will continuously read the
EEPROM if RBD is set to ‘0’. The remaining bits in this
register must be set to ‘0’.
TABLE V. Analog Control Registers.
Instruction
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
0
0
0
A3
A2
A1
A0
EEPROM Mode
0
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
2
3
4
5
6
7
8
9
RST
0
0
0
0
FD
0
AC7
0
0
FG7
CG7
FZ7
CZ7
L7
S7
CSE
0
0
0
0
US2
0
AC6
VP2
IB2
FG6
CG6
FZ6
CZ6
L6
S6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Reserved
Reserved
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Control Register 1
F3
0
OS3
0
AC3
0
0
FG3
CG3
FZ3
CZ3
L3
S3
F2
0
OS2
G2
AC2
VN2
IA2
FG2
CG2
FZ2
CZ2
L2
S2
F1
0
OS1
G1
AC1
VN1
IA1
FG1
CG1
FZ1
CZ1
L1
S1
F0
RBD
OS0
G0
AC0
VN0
IA0
FG0
CG0
FZ0
CZ0
L0
S0
Fault Status Register
Control Register 2
Over/Under-Scale Register
PGA Gain
Alarm Config. Register
PGA Input Config. Register
I
REF
Output Config. Register
Fine I
REF
Adjust Register
Coarse I
REF
Adjust Register
Fine Zero Adjust Register
Coarse Zero Adjust Register
Linearization Adjust Register
Checksum Register
US1
0
AC5
VP1
IB1
FG5
CG5
FZ5
CZ5
L5
S5
US0
0
AC4
VP0
IB0
FG4
CG4
FZ4
CZ4
L4
S4
10
11
12
13
14
15
Read/Write Operation
Data Bit
Assert CS2
Ignore Serial Data/A
BIT
F0
F1
F2
F3
TABLE VI. Register 3, Fault Status Register.
FAULT MODE
Negative Input Exceeds Positive Limit.
Negative Input Exceeds Negative Limit.
Positive Input Exceeds Positive Limit.
Positive Input Exceeds Negative Limit.
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