參數(shù)資料
型號: XWM8181CDW
廠商: Wolfson Microelectronics
英文描述: 12-bit 2MSPS Serial Output CIS/CCD Digitiser
中文描述: 12位2MSPS串行輸出獨(dú)聯(lián)體/防治荒漠化公約數(shù)字化儀
文件頁數(shù): 5/14頁
文件大?。?/td> 150K
代理商: XWM8181CDW
Advanced Information
WM8181
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 January 2000
5
TEST CHARACTERISTICS
AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, T
A
= 0 to 70
°
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL SPECIFICATION
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
OVERALL SYSTEM SPECIFICATION
Supply Currents
Total analogue supply current –
active
V
IH
V
IL
0.8
DVDD
V
V
μA
μA
pF
0.2
DVDD
<1
<1
5
I
OH
= 1mA
I
OL
= -1mA
DVDD - 0.5
V
V
μA
0.5
<1
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
21
19
2
1
<1
<1
mA
mA
mA
mA
μA
μA
Total digital supply current –
active
Supply current – disabled
MCLK
VSMP
DOUT
t
MCLKH
t
MCLKL
t
PER
t
VSMPSU
t
VSMPH
SAMPLE n
t
PD
n-2 D[11]
n-2 D[10]
n-2 D[9]
Figure 1 Clock Inputs and Data Output
TEST CHARACTERISTICS
AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, T
A
= 0 to 70
°
C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
t
PER
t
MCLKH
t
MCLKL
t
VSMPSU
t
VSMPH
t
PD
TEST CONDITIONS
MIN
41.7
16
16
10
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
Maximum MCLK period
MCLK high
MCLK low
VSMP data set-up time
VSMP data hold time
MCLK to DOUT
propagation delay
MCLK to DOUT
propagation delay
AVDD = DVDD = 5V
10
t
PD
AVDD = DVDD = 3.3V
15
ns
Note: Parameters are measured at 50% of the rising/falling edge.
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