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參數(shù)資料
| 型號(hào)： | XWM8706EDS |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24-bit, 192kHz Stereo DAC with Volume Control |
| 中文描述： | 24位，192kHz的帶有音量控制的立體聲DAC |
| 文件頁(yè)數(shù)： | 18/24頁(yè) |
| 文件大?。?/td> | 237K |
| 代理商： | XWM8706EDS |
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WM8706
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
18
POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to V
MID
and selects a low power
mode. All trace of the previous input samples is removed, and all register settings are cleared.
When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat
it
’
s power-on initialisation sequence.
REGISTER ADDRESS
010
DAC Control
BIT
2
LABEL
PWDN
DEFAULT
0
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
1: Power Down Mode
Table 12 Powerdown Control
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8706 has a fully featured digital audio interface that is a superset of that contained in
the WM8716. Interface format is selected via the IW[2:0] register bits in register M2 and the I
S
register bit in M3.
REGISTER ADDRESS
010
DAC Control
Table 13 Interface Format Controls
BIT
5:3
LABEL
IW[2:0]
DEFAULT
000
DESCRIPTION
Interface format Select
REGISTER ADDRESS
011
Interface Control
Table 14 Interface Format Control
BIT
0
LABEL
I
2
S
DEFAULT
0
DESCRIPTION
Interface format Select
IW2
I
2
S
IW1
IW0
AUDIO INTERFACE DESCRIPTION **
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
16 bit right justified mode
20 bit right justified mode
24 bit right justified mode
24 bit left justified mode
16 bit I
2
S mode
24 bit I
2
S mode
20 bit I
2
S mode
20 bit left justified (MSB first) mode
16 bit DSP mode
20 bit DSP mode
24 bit DSP mode
32 bit DSP mode
16 bit left justified mode
Table 15 Audio Data Input Format
Note:
** In all modes, the data is signed 2
’
s complement. The digital filters always input 24-bit data. If
the DAC is programmed to receive 16 or 20 bit data, the WM8706 pads the unused LSBs with
zeros. If the DAC is programmed into 32 bit mode, the 4 LSBs are ignored.
SELECTION OF LRCIN POLARITY
In left justified, right justified or I
2
S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 4,
Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and
right channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
011
Interface Control
BIT
1
LABEL
LRP
DEFAULT
0
DESCRIPTION
LRCIN Polarity (normal)
0 : normal LRCIN polarity
1: inverted LRCIN polarity
Table 16 LRCIN Polarity Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XWM8711EDS | Internet Audio DAC with Integrated Headphone Driver |
| XWM8721EDS | Internet Audio DAC with Integrated Headphone Driver |
| XWM8722EDS | Stereo DAC with Integrated Tone Generator and Line/Variable Level Outputs |
| XWM8728EDS | 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support |
| XWM8729ED | 24-bit, 192kHz Stereo DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XWM8711EDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Internet Audio DAC with Integrated Headphone Driver |
| XWM8721EDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Internet Audio DAC with Integrated Headphone Driver |
| XWM8721EDS/R | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Internet Audio DAC with Integrated Headphone Driver |
| XWM8722EDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Stereo DAC with Integrated Tone Generator and Line/Variable Level Outputs |
| XWM8728EDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:24-bit, 192kHz Stereo DAC with Volume Control |
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