參數(shù)資料
型號： XWM9708CDS
廠商： Wolfson Microelectronics
元件分類： Codec
英文描述： AC97 Revision 2.1 Audio Codec
中文描述： AC97音頻編解碼器2.1版
文件頁數(shù)： 17/28頁
文件大小： 205K
代理商： XWM9708CDS
Advanced Information
WM9708
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 April 2001
17
SYNC
BITCLK
SDATAIN
THE WM9707 SAMPLES SYNC ASSERTION HERE
AC
’
97 CONTROLLER SAMPLES FIRST
SDATA_IN BIT OF FRAME HERE
END OF PREVIOUS AUDIO FRAME
CODEC
READY
SLOT (1)
SLOT (2)
Figure 12 Start of an Audio Input Frame
A new audio input frame begins with a low to high transition of SYNC as shown in Figure 12. SYNC
is incident with the rising edge of BITCLK. On the immediately following falling edge of BITCLK,
AC
’
97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link
are aware of the start of a new audio frame. On the next rising of BITCLK, AC
’
97 transitions
SDATAIN into the first bit position of slot 0 (
“
Codec Ready
”
bit). Each new bit position is presented
to AC-link on a rising edge of BITCLK, and subsequently sampled by the AC
’
97 Controller on the
following falling edge of BITCLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDATAIN
’
s composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned
and/or unassigned time slots) stuffed with 0s by the WM9708. SDATAIN should be sampled on the
falling edges of BITCLK.
SLOT 1: STATUS ADDRESS PORT
The status port is used to monitor status for the WM9708 functions including, but not limited to, mixer
settings, and power management.
Audio input frame slot 1 echoes the control register index, for historical reference, for the data to
be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9708 during slot
0).
STATUS ADDRESS PORT BIT ASSIGNMENTS
:
Bit (19)
Bit (18:12)
RESERVED (stuffed with 0s)
Control register index (echo of register index for which data is
being returned)
Variable sample rate SLOTREQ bits.
RESERVED (stuffed with 0s)
Bit (11:2)
Bit (1:0)
The first bit (MSB) generated by the WM9708 is always stuffed with a 0. The following 7 bit positions
communicate the associated control register address. The next 10 bits support the AC
’
97 Rev 2.1
variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by AC
’
97.
In VRA the slot requests in slot 1 (bits 11-3) are always valid regardless of slot tag.
SLOT 2: STATUS DATA PORT
The status data port delivers 16-bit control register read data.
Bit (19:4)
Control register read data (stuffed with 0s if tagged invalid by
WM9701)
RESERVED (stuffed with 0s)
Bit (3:0)
If slot 2 is tagged invalid by the WM9708, then the entire slot will be stuffed with 0s by the WM9708.
SLOT 3: PCM RECORD LEFT CHANNEL
Audio input frame slot 3 is the left channel output of the WM9708
’
s input Mux, post-ADC.
The
WM9708 sends out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions
with 0s to fill out its 20-bit time slot.
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