參數(shù)資料
型號(hào)： Z5380
廠商： ZiLOG, Inc.
英文描述： Small Computer System Interface(小型計(jì)算機(jī)系統(tǒng)接口(SCSI)控制器)
中文描述： 小型計(jì)算機(jī)系統(tǒng)接口（小型計(jì)算機(jī)系統(tǒng)接口（的SCSI）控制器）
文件頁(yè)數(shù)： 12/37頁(yè)
文件大小： 409K
代理商： Z5380
12
Z5380 SCSI
PS97SCC0100
Z
ILOG
FUNCTIONAL DESCRIPTION
(Continued)
For send operations, the End of DMA bit is set when the
DMA finishes its transfers, but the SCSI transfer may still be
in progress. If connected as a Target, /REQ and /ACK
should be sampled until both are False. If connected as an
Initiator, a phase change interrupt is used to signal the
completion of the previous phase. It is possible for the
Target to request additional data for the same phase. In
this case, a phase change will not occur and both /REQ
and /ACK are sampled to determine when the last byte was
transferred.
SCSI Bus Reset Interrupt
The Z5380 generates an interrupt when the /RST signal
transitions to True. The device releases all bus signals
within a bus-clear delay of this transition. This interrupt also
occurs after setting the Assert /RST bit (Initiator Command
Register, bit 7). This interrupt cannot be disabled. (
Note:
/RST is not latched in bit 7 of the Current SCSI Bus Status
Register and is not active when this port is read. For this
case, the Bus Reset interrupt is determined by default.)
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
18 and 19, respectively.
Figure 18. Bus and Status Register
Figure 19. Current SCSI Bus Status Register
Parity Error Interrupt
An Interrupt is generated for a received parity error if the
Enable Parity Check (bit 5) and the Enable Parity Interrupt
(bit 4) bits are set (1) in the Mode Register. Parity is
checked during a read of the Current SCSI Data Register
and during a DMA receive operation. A parity error can be
detected without generating an interrupt by disabling the
Enable Parity Interrupt bit and checking the Parity Error
flag (Bus and Status Register, bit 5).
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
20 and 21, respectively.
Figure 20. Bus and Status Register
D7
D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
X
0
1
X
0
X
X
D7
D0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
X
X
X
X
X
X
X
X
D7
D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
X
1
1
1
0
X
X
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