參數(shù)資料
型號(hào)： Z53C8003VSC
廠商： ZILOG INC
元件分類： 總線控制器
英文描述： SMALL COMPUTER SYSTEM INTERFACE (SCSI)
中文描述： SCSI BUS CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 18/40頁(yè)
文件大?。?/td> 447K
代理商： Z53C8003VSC
18
Z53C80 SCSI
PS97SCC0200
Z
ILOG
FUNCTIONAL DESCRIPTION
(Continued)
Pseudo DMA Mode.
To avoid monitoring and asserting
the request/acknowledgment handshake signals for
programmed I/O transfers, the system may be designed to
implement a pseudo DMA mode. This mode is implemented
by programming the Z53C80 to operate in the DMA mode,
but using the CPU to emulate the DMA handshake. DRQ
may be detected by polling the DMA Request bit (bit 6) in
the Bus and Status Register, by sampling the signal
through an external port, or by using it to generate a CPU
interrupt. Once DRQ is detected, the CPU can perform a
read or write data transfer. This CPU read/write is externally
decoded to generate the appropriate /DACK and /RD or
/WR signals.
Often, external decoding logic is necessary to generate
the /CS signal. This same logic may be used to generate
/DACK at no extra cost and provide an increased
performance in programmed I/O transfers.
Halting a DMA Operation.
The EOP signal is not the only
way to halt a DMA transfer. A bus phase mismatch or a
reset of the DMA MODE bit (Mode Register, bit 1) can also
terminate a DMA cycle for the current bus phase.
Using the /EOP Signal.
If /EOP is used, it should be
asserted for at least 50 ns while /DACK and /RD or /WR are
simultaneously active. Note, however, that if /RD or /WR is
not active, an interrupt is generated, but the DMA activity
continues. The /EOP signal does not reset the DMA MODE
bit. Since the /EOP signal can occur during the last byte
sent to the Output Data Register, the /REQ and /ACK
signals are monitored to ensure that the last byte has
transferred.
Bus Phase Mismatch Interrupt.
A bus phase mismatch
interrupt is used to halt the transfer if operating as an
Initiator. Using this method frees the host from maintaining
a data length counter and frees the DMA logic from
providing the /EOP signal. If performing an Initiator send
operation, the Z53C80 requires /DACK to cycle before
/ACK goes inactive. Since phase changes cannot occur if
/ACK is active, either /DACK must be cycled after the last
byte is sent or the DMA Mode bit must be reset in order to
receive the phase mismatch interrupt.
Resetting the DMA MODE Bit.
A DMA operation may be
halted at any time simply by resetting the DMA Mode bit.
It is recommended that the DMA Mode bit be reset after
receiving an /EOP or bus phase-mismatch interrupt. The
DMA Mode bit must then be set before writing any of the
start DMA registers for subsequent bus phases.
If resetting the DMA Mode bit is used instead of /EOP for
Target role operation, then care must be taken to reset this
bit at the proper time. If receiving data as a Target device,
the DMA Mode bit must be reset once the last DRQ is
received and before /DACK is asserted to prevent an
additional /REQ from occurring. Resetting this bit causes
DRQ to go inactive. However, the last byte received
remains in the Input Data Register and may be obtained
either by performing a normal CPU read or by cycling
/DACK and /RD. In most cases, /EOP is easier to use when
operating as a Target device.
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