參數(shù)資料
型號(hào)： Z53C8003VSC
廠商： ZILOG INC
元件分類： 總線控制器
英文描述： SMALL COMPUTER SYSTEM INTERFACE (SCSI)
中文描述： SCSI BUS CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 5/40頁(yè)
文件大?。?/td> 447K
代理商： Z53C8003VSC
5
Z53C80 SCSI
Z
ILOG
PS97SCC0200
PIN DESCRIPTION
Microprocessor Bus
A2-A0
Address Lines (Input).
Address lines are used to
access all internal registers with /CS, /IOR, and /IOW.
/CS
/Chip Select (Input, active Low)./CS, in conjunction
with /RD or /WR, enables the internal register selected by
A2-A0, to be read from or write to. /CS and /DACK must
never be active simultaneously.
/DACK
/DMA Acknowledge Input, active Low)./DACK, in
conjunction with /IOR and /IOW, is used to enable reading
or writing the SCSI I/O Data Registers when in the DMA
Mode. When the DRQ has acknowledged that the byte has
been successfully transferred to or from the DMA controller,
this signal is asserted. /DACK and /CS must never be
active simultaneously.
DRQ
DMA Request (Output, active High).This signal is
asserted when the chip is ready to transfer a data byte to
and from the DMA controller. The DMA Request will be
asserted only if the DMA Mode bit (Register 2, Bit 1) is set.
The transfer is complete upon reception of /DACK.
D7-D0
Data Lines (Bi-directional; Tri-State, active High).
The Data Bus lines carry data and commands to and from
SCSI. D7 is the most significant bit of this bus.
/EOP
/End of Process (Input, active Low). To terminate a
DMA transfer, this signal is asserted. The current byte will
be transferred but no additional bytes will be requested if
asserted during a DMA cycle. /EOP can be used to
generate an interrupt when it is received from a DMA
Controller.
/IOR
/I/O Read (Input, active Low). This signal is used to
read an internal register selected by /CS and A2-A0. The
Input Data Register can also be selected by this signal
when /DACK is active during DMA transfers.
/IOW
/I/O Write (Input, active Low). This signal is used to
write to an internal register selected by /CS and A2-A0. The
Output Data Register can also be selected by this signal
when used with /DACK during DMA transfers.
IRQ
Interrupt Request Output, active High). RQ alerts the
microprocessor of an error condition or an event completion.
Most of the interrupts are individually maskable.
READY
Ready (Output, active High). This signal can be
used to control the data transfer handshaking of block
mode DMA transfers. READY is asserted to indicate that
the chip is ready to transfer data and remains false after a
transfer until the chip is ready for another DMA transfer.
READY is always asserted when the DMA Mode Bit is a
zero.
/RESET
/Reset (Input, active Low). /RESET clears all
registers and has no effect upon the SCSI /RST signal.
Therefore it does not reset the SCSI bus.
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