參數(shù)資料
型號: Z80181
廠商: ZiLOG, Inc.
英文描述: SMART ACCESS CONTROLLER (SAC⑩)
中文描述: 智能門禁控制器(國資委⑩)
文件頁數(shù): 14/74頁
文件大?。?/td> 540K
代理商: Z80181
2-14
Z80181
S
MART
A
CCESS
C
ONTROLLER
SAC
Zilog
DS971800500
FUNCTIONAL DESCRIPTION
(Continued)
Baud Rate
Generator
Channel
Registers
Internal
Control
Logic
Interrupt
Control
Logic
10 X 19
Frame
Status
FIFO
Channel
Discrete
Control
& Status
Interrupt
Control
Lines
} Serial Data
} Channel Clocks
/SYNC
/Wait
Modem, DMA,
or Other
Controls
Internal BUS
Z85C30 Serial Communication Controller
Logic Unit
This logic unit provides the user with a multi-protocol serial
I/O channel that is completely compatible with the two
channel Z85C30 SCC with the following exceptions:
Their basic functions as serial-to-parallel and parallel-to-
serial converters can be programmed by the CPU for a
broad range of serial communications applications. This
logic unit is capable of supporting all common asynchro-
nous and synchronous protocols (Monosync, Bisync, and
SDLC/HDLC, byte or bit oriented - Figure 4).
On the discrete version of the SCC (dual channel version),
there are two registers shared between channels A and B,
and two registers whose functions are different by chan-
nel. These are: WR2, WR9 (shared registers), and RR2 and
RR3 (different functionality).
Following are the differences in functionality:
I
RR2
- Returns Unmodified Vector or modified vector
depends on the status of “VIS” (Vector Include Status)
bit in WR9.
Figure 4. SCC Block Diagram
I
RR3
- Returns IP status (Ch.A side).
I
WR9
- Ch.B Software Reset command has no effect.
The PCLK for the SCC is connected to PHI (System clock),
the /INT signal is connected to /INT0 signal internally
(requires external pull-up resistor) and SCC is reset when
/RESET input becomes active. Interrupt from the SCC is
handled through Mode 2 interrupt. During the interrupt
acknowledge cycle, the on-chip SCC interface circuit
inserts two wait states automatically.
Z84C30 Counter/Timer Logic Unit
This logic unit provides the user with four individual 8-bit
Counter/Timer Channels that are compatible with the
Z84C30 CTC (Figure 5). The Counter/Timers are pro-
grammed by the CPU for a broad range of counting and
timing applications. Typical applications include event
counting, interrupt and interval counting, and serial baud
rate clock generation.
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