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參數(shù)資料
| 型號： | Z80181 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | SMART ACCESS CONTROLLER (SAC⑩) |
| 中文描述： | 智能門禁控制器（國資委⑩） |
| 文件頁數(shù)： | 16/74頁 |
| 文件大小： | 540K |
| 代理商： | Z80181 |
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2-16
Z80181
S
MART
A
CCESS
C
ONTROLLER
SAC
Zilog
DS971800500
FUNCTIONAL DESCRIPTION
(Continued)
Recommended characteristics of the crystal and the val-
ues for the capacitor are as follows (the values will change
with crystal frequency).
Type of crystal: Fundamental, parallel type crystal
(AT cut is recommended).
Frequency tolerance: Application dependent.
CL, Load capacitance: Approximately 22 pF
(acceptable range is 20-30 pF)
Rs, equivalent-series resistance:
≤
30 Ohms
Drive level: 10 mW (for
≤
10 MHz crystal) 5 mW
(for
≥
10 MHz crystal)
C
IN
= C
OUT
= 15 ~ 22 pF.
Chip Select Signals
The SAC has two chip select (/RAMCS, /ROMCS) pins.
/ROMCS is the chip select signal for ROM and /RAMCS is
the chip select signal for RAM. The boundary value for
each chip select signal is 8 bits wide allowing all memory
accesses with addresses less than or equal to this bound-
ary value. This causes assertion of the corresponding /CS
pin. These features are controlled through the RAM upper
boundary address register (I/O address EAh), RAM lower
boundary address register (I/O address EBh) and ROM
upper boundary address register (I/O address ECh).
Programming
The following subsections explain and define the parame-
ters for I/O Address assignments, I/O Control Register
Addresses and all pertinent Timing parameters.
I/O Address Assignment
The SAC has 78 internal 8-bit registers to control on-chip
peripherals and features. Sixty-four registers out of 78
registers are occupied by the Z181 MPU control registers;
two for SCC control registers, four for PIA control registers,
four for the Counter/Timer, three for RAM/ROM configura-
tion (memory address boundaries) and one for SAC’s
system control. The SAC’s I/O addresses are listed in
Table 1. These registers are assigned in the SAC’s I/O
addressing space and the I/O addresses are fully de-
coded from A7-A0 and have no image.
These two signals are generated by decoding address
lines A19-A12. Note that glitches may be observed on the
/RAMCS and /ROMCS signals because the address de-
coding logic decodes only A19-A12, without any control
signals.
Bit D5 of the System Configuration Register allows the
option of disabling the /ROMCS signal. This feature is used
in systems which, for example, have a shadow RAM.
However, prior to disabling the /ROMCS signal, the ROMBR
and RAMLBR registers must be re-initialized from their
default values.
For more details, please refer to “Programming section”.
ROM Emulator Mode
To ease development, the SAC has a mode to support
“ROM emulator” development systems. In this mode, a
read data from on-chip registers (except Z181 MPU on-
chip registers) are available (data bus direction set to
output) to make data visible from the outside, so that a
ROM Emulator/Logic Analyzer can monitor internal trans-
actions. Otherwise, a read from an internal transaction is
not available to the outside (data bus direction set to Hi-Z
status). Mode selection is made through the D1 bit in the
System Configuration Register (I/O Address: EDh).
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