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參數(shù)資料
| 型號： | Z80181 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | SMART ACCESS CONTROLLER (SAC⑩) |
| 中文描述： | 智能門禁控制器（國資委⑩） |
| 文件頁數(shù)： | 4/74頁 |
| 文件大?。?/td> | 540K |
| 代理商： | Z80181 |
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2-4
Z80181
S
MART
A
CCESS
C
ONTROLLER
SAC
Zilog
DS971800500
CPU SIGNALS
Pin Name
Pin Number
Input/Output, Tri-State
Function
A19 - A0
4-17, 19-21,
64, 65, 91
I/O, Active 1
Address Bus.
A19 - A0 form a 20-bit address bus which
specifies I/O and memory addresses to be accessed.
During the refresh period, addresses for refreshing are
output. The address bus enters a high-impedance state
during Reset and external bus acknowledge cycles. The
bus is an input when the external bus master is accessing
the on-chip peripherals. Address line A18 is multiplexed
with the output of PRT Channel 1 (T
OUT
, selected as address
output on Reset).
D0-D7
22-29
I/O, Active 1
8-Bit Bidirectional Data Bus.
When the on-chip CPU is
accessing on-chip peripherals, these lines are outputs
and hold the data to/from the on-chip peripherals.
/RD
89
I/O, Active 0
Read Signal.
CPU read signal for accepting data from
memory or I/O devices. When an external master is ac-
cessing the on-chip peripherals, it is an input signal.
/WR
88
I/O, Active 0
Write Signal.
This signal is active when data to be stored
in a specified memory or peripheral device is on the MPU
data bus. When an external master is accessing the on-
chip peripherals, it is an input signal.
/MREQ
85
I/O, tri-state, Active 0
Memory Request Signal.
When an effective address for
memory access is on the address bus, /MREQ is active.
This signal is analogous to the /ME signal of the Z64180.
/IORQ
84
I/O, tri-state, Active 0
I/O Request Signal.
When addresses for I/O are on the
lower 8 bits (A7-A0) of the address bus in the I/O operation,
“0” is output. In addition, the /IORQ signal is output with the
/M1 signal during the interrupt acknowledge cycle to
inform peripheral devices that the interrupt response vec-
tor is on the data bus. This signal is analogous to the /IOE
signal of the Z64180.
/M1
87
I/O, tri-state, Active 0
Machine Cycle “1”.
/MREQ and /M1 are active together
during the operation code fetch cycle. /M1 is output for
every opcode fetch when a two byte opcode is executed.
In the maskable interrupt acknowledge cycle, this signal is
output together with /IORQ. It is also used with
/HALT and ST signal to decode the status of the CPU
Machine cycle. This signal is analogous to the /LIR signal
of the Z64180.
/RFSH
83
Out, tri-state, Active 0
The Refresh Signal.
When the dynamic memory
refresh address is on the low order 8-bits of the address
bus (A7 - A0), /RFSH is active along with the /MREQ signal.
This signal is analogous to the /REF signal of the Z64180.
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