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參數(shù)資料
| 型號： | Z86C02 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Cost Effective ,512-Byte ROM CMOS Z8 Microcontroller(帶512字節(jié)ROM的CMOS 微控制器) |
| 中文描述： | 成本效益,512 - ROM的字節(jié)的CMOS Z8微控制器（帶光盤的512字節(jié)的CMOS微控制器） |
| 文件頁數(shù)： | 19/37頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | Z86C02 |
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Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
19
1
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z86C02/E02/L02 devices to enhance the standard
Z8
core architecture to provide the user with increased de-
sign flexibility.
RESET.
This function is accomplished by means of a Pow-
er-On Reset or a Watch-Dog Timer Reset. Upon power-
up, the Power-On Reset circuit waits for T
POR
ms, plus 18
clock cycles, then starts program execution at address
000C (Hex) (Figure 11). The control registers' reset value
is shown in Table 4.
Power-On Reset (POR).
A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V
CC
and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the four
following conditions:
I
Power bad to power good status
I
Stop-Mode Recovery
I
WDT time-out
I
WDH time-out (in Halt Mode)
I
WDT time-out (in Stop Mode)
Watch-Dog Timer Reset.
The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Figure 11. Internal Reset Configuration
POR
(Cold Start)
P27
(Stop Mode)
Delay Line
T
POR
ms
18 CLK
Reset Filter
Chip
Reset
XTAL OSC
INT OSC
Table 4. Control Register
Reset Condition
Addr Reg.
FF
FE
FD
FC
FB
FA
D7 D6 D5 D4 D3 D2 D1 D0 Comments
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLAGS U
U
U
U
U
IMR
0
U
U
U
U
IRQ
U
U
0
0
0
SPL
GPR
RP
0
0
0
U
U
0
0
0
0
U
U
0 IRQ3 is used
for positive
edge
detection
U
1
0 P2 open-drain
1 Inputs after
reset
0
U
0
U
U
0
F9
F8
F7*
F6*
IPR
P01M
P3M
P2M
U
U
U
1
U
U
U
1
U
U
U
1
U
0
U
1
U
U
U
1
U
U
U
1
U
0
0
1
F3
F2
F1
Note:
*Registers are not reset after a STOP-Mode Recovery
using P27 pin. A subsequent reset will cause these control
registers to be reconfigured as shown in Table 4 and the
user must avoid bus contention on the port pins or it may
affect device reliability.
PRE1
T1
TMR
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
0
U
0
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