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參數(shù)資料
| 型號： | Z86C02 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Cost Effective ,512-Byte ROM CMOS Z8 Microcontroller(帶512字節(jié)ROM的CMOS 微控制器) |
| 中文描述： | 成本效益,512 - ROM的字節(jié)的CMOS Z8微控制器（帶光盤的512字節(jié)的CMOS微控制器） |
| 文件頁數(shù)： | 21/37頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | Z86C02 |
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Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
21
1
Stack Pointer.
The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 60 gen-
eral-purpose registers. It is set to 00Hex after any reset.
General-Purpose Registers (GPR).
These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
CC
voltage-specified operating range.
Note:
Register R254 has been designated as a general-purpose
register. But is set to 00Hex after any reset.
Counter/Timer.
There is an 8-bit programmable
counter/timers (T1), each driven by its 6-bit programmable
prescaler. The T1 prescaler is driven by internal or external
clock sources. (Figure 15).
The 6-bit prescaler divide the input frequency of the clock
source by any integer number from 1 to 64. The prescaler
drives its counter, which decrements the value (1 to 256)
that has been loaded into the counter. When both counter
and prescaler reach the end of count, a timer interrupt re-
quest IRQ5 (T1) is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters are
also programmed to stop upon reaching zero (Single-Pass
mode) or to automatically reload the initial value and con-
tinue counting (Modulo-N Continuous Mode).
The counter, but not the prescaler, is read at any time with-
out disturbing its value or count mode. The clock source for
T1 is user-definable and is either the internal microproces-
sor clock divided by four, or an external signal input
through Port 3. The Timer Mode register configures the ex-
ternal timer input (P31) as an external clock, a trigger input
that is retriggerable or non-retriggerable, or used as a gate
input for the internal clock.
Figure 14. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7
r6
r5
r4
R253
(Register Pointer)
I/O Ports
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
r3
r2
r1
r0
Register Group 1
Register Group 0
R15 to R0
Register Group F
R15 to R4
R3 to R0
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
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