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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
38
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION
(Continued)
0, 1, 2, and 3, and low-EMI oscillator. The
PCON
register
is located in the expanded register file at Bank F, location
00h
(Figure 25).
Comparator Output Port 3 (D0).
Bit
0
controls the com-
parator use in Port 3. A
1
in this location brings the com-
parator outputs to
P34
and
P37
, and a
0
releases the Port to
its standard I/O configuration. The default value is
0
.
Port 1 Open-Drain (D1).
Port 1 can be configured as an
open-drain by resetting this bit (
D1 = 0
) or configured as
push-pull active by setting this bit (
D1 = 1
). The default val-
ue is
1
. The user must set
D1 = 1
for devices in 28-pin pack-
ages.
Port 0 Open-Drain (D2).
Port 0 can be configured as an
open-drain by resetting this bit (
D2 = 0
) or configured as
push-pull active by setting this bit (
D2 = 1
). The default val-
ue is
1
.
Low-EMI Port 0 (D3).
Port 0 can be configured as a low-
EMI port by resetting this bit (
D3 = 0
) or configured as a
Standard Port by setting this bit (
D3 = 1
). The default value
is
1
.
Low-EMI Port 1 (D4).
Port 1 can be configured as a low-
EMI port by resetting this bit (
D4 = 0
) or configured as a
Standard Port by setting this bit (
D4 = 1
). The default value
is
1
. The user must set
D4 = 1
for devices in 28-pin packages.
Note:
For emulator, this bit must be set to
1
.
Low-EMI Port 2 (D5).
Port 2 can be configured as a low-
EMI port by resetting this bit (
D5 = 0
) or configured as a
Standard Port by setting this bit (
D5 = 1
). The default value
is
1
.
Low-EMI Port 3 (D6).
Port 3 can be configured as a low-
EMI port by resetting this bit (
D6 = 0
) or configured as a
Standard Port by setting this bit (
D6 = 1
). The default value
is
1
.
Low-EMI OSC (D7).
This bit of the
PCON
Register con-
trols the low-EMI noise oscillator. A
1
in this location con-
figures the oscillator,
DS
,
AS
and
R/W
with standard drive,
while a
0
configures the oscillator,
DS
,
AS
and
R/W
with
low noise drive. The low-EMI mode reduces the drive of
the oscillator (OSC). The default value is
1
.
Note:
Maximum external clock frequency of 4 MHz when run-
ning in the
low-EMI
oscillator mode.
Low-EMI Emission.
The Z8 can be programmed to operate
in a low-EMI emission mode in the
PCON
register. The os-
cillator and all I/O ports can be programmed as low-EMI
emission mode independently. Use of this feature results in:
The pre-drivers slew rate reduced to 10 ns (typical)
Low-EMI output drivers exhibit resistance of 200 Ohms
(typical)
Low-EMI Oscillator
Internal
SCLK/TCLK = XTAL
operation limited to a
maximum of 4 MHz–250 ns cycle time, when
LOW
EMI OSCILLATOR
is selected and system clock (
SCLK
= XTAL
,
SMR REGISTER BIT D1 = 1
)
Stop-Mode Recovery Register (SMR).
This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figures 26 and 27). All bits are
WRITE ONLY
, except bit
7
, which is
READ
ONLY
. Bit
7
is a flag bit that is hardware set on the condition of
STOP
recovery and
RESET
by a power-on cycle. Bit
6
controls
whether a low level or a high level is required from the re-
covery source. Bit
5
controls the reset delay after recovery.
Bits 2, 3, and 4, or the
SMR
register, specify the source of
the Stop-Mode Recovery signal. Bits
0
and
1
determine the
time-out period of the
WDT
. The
SMR
is located in Bank
F of the Expanded Register Group at address
0BH
.
Figure 25. Port Configuration Register (PCON)
(WRITE ONLY)
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
D7
D6
D5
D4
D3
D2
D1
D0
PCON (FH) 00H
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
*Default Setting After Reset
Must be set to one for devices
in 28-pin packages
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
0 Port 1 Low EMI
1
Port 1
Standard*