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參數(shù)資料
| 型號： | Z86C36 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機(jī)的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 45/70頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | Z86C36 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
DS007601-Z8X0499
P R E L I M I N A R Y
45
a
0
to the
EFR
bit in
CNTLA
is the only way to clear these
latches. In other words, when an error bit reaches the top
of the FIFO, it sets an error latch. If the FIFO contains more
data and the software reads the next byte out of the FIFO,
the error latch remains set until the software writes a
0
to
the
EFR
bit. The error bits are cumulative, so if additional
errors are in the FIFO they set any unset error latches as they
reach the top.
Baud Rate Generator.
The baud rate generator features
two modes. The first provides a dual set of fixed clock di-
vide ratios as defined in
CNTLB
. In the second mode, the
BRG
is configured as a sixteen-bit down counter that divides
the processor clock by the value in a software accessible,
sixteen-bit, time-constant register. As a result, virtually any
frequency can be created by appropriately selecting the
main processor clock frequency. The
BRG
can also be dis-
abled in favor of the
SCLK
.
The Receiver and Transmitter subsequently divide the out-
put of the Baud rate Generator (or the signal from the
CLK
pin) by 1, 16 or 64 under the control of the
DR
bit in the
CNTLB
register and the
X1
bit in the ASCI Extension Con-
trol Register (
ASEXT
).
RESET.
During
RESET
, the ASCI is forced to the following
conditions:
FIFO Empty
All Error Bits Cleared (including those in the FIFO)
Receive Enable Cleared (
CNTLA BIT 6 = 0
)
Transmit Enable Cleared (
CNTLA BIT 5 = 0
)
Figure 31. ASCI Interface Diagram
Internal Address/Data Bus
ASCI Transmit Data Register
TDR (Bank:Ah,Addr :01h)
ASCI Status FIFO/Register
STAT (Bank:Ah,Addr:08h)
ASCI Transmit Shift Register
TSR
ASCI Receive Data FIFO
RDR (Bank:Ah,Addr:02h)
ASCI Receive Shift Register
RSR
ASCI Control Register A
CNTLA (Bank:Ah,Addr:03h)
Accessible
ASCI Control Register B
CNTLB (Bank:Ah,Addr:04h)
ASCI Extension Control Reg.
ASEXT (Bank:Ah,Addr:05h)
ASCI Time Constant High
ASTCH (Bank:Ah,Addr:07h)
ASCI Time Constant Low
ASTCL (Bank:Ah,Add:06h)r
Baud Rate Generator
SCLK
(P37) TX
(P30) RX
ASCI
Control
IRQ3
Interrupt Request
**
**
Note: **Not Program
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z86C3600ZEM | 功能描述:仿真器/模擬器 Z8 C36 ICEBOX RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| Z86C40 | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:CMOS Z8 CONSUMER CONTROLLER PROCESSOR |
| Z86C4000ZDV | 功能描述:仿真器/模擬器 Z86C40 PLCC Em Pod RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| Z86C4001ZDV | 功能描述:仿真器/模擬器 Z86C40 PLCC Em Pod RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| Z86C4016FEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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