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參數(shù)資料
| 型號： | Z86U18 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | USB Device Controller(鍵盤及其它外設(shè)的理想的USB微控制器) |
| 中文描述： | USB設(shè)備控制器（鍵盤及其它外設(shè)的理想的的USB微控制器） |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 311K |
| 代理商： | Z86U18 |
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Z86E18/U18
Zilog
1.5 MBPS USB Device Controller for Keyboards and HID-Class Peripherals
DS97KEY2301
P R E L I M I N A R Y
17
1
Power-On-Reset
(POR)
.
POR timing is a function of the
system clock. A timer circuit is triggered by the system os-
cillator and is used for the Power-On Reset (POR) timer
function. The POR time allows V
and the oscillator circuit
to stabilize before instruction execution begins. POR peri-
od is defined as:
The POR timer circuit is a one-shot timer triggered by pow-
er fail to Power OK status. The POR time is a nominal 0.17
ms at 6 MHz. The POR time is bypassed after Stop-Mode
Recovery.
HALT.
HALT turns off the internal CPU clock, but not the
oscillator. The counter/timer and external interrupts IRQ0,
IRQ1, IRQ2, and IRQ3 remain active. The Z86U18 recov-
ers by interrupts, either externally or internally.
STOP.
This instruction turns off the internal clock and ex-
ternal resonator oscillation. It reduces the standby current
to less than 10
μ
A. The STOP Mode is terminated by a RE-
SET, USB RESET, P20–P26, or P30–P33 (Figure 17).
This termination causes the processor to restart the appli-
cation program at the address 000C (HEX). In order to en-
ter STOP (or HALT) Mode, it is necessary to first flush the
instruction pipeline to avoid suspending execution in mid-
instruction. To flush the pipeline, the user must execute a
NOP (opcode=FFH) immediately before the appropriate
sleep instruction, such as:
T
POR
(ms) = 1024 clock
≈
0.17 ms (when clock is 6 MHz)
FF
6F
NOP
STOP
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
FF
7F
NOP
HALT
Figure 17. STOP-Mode Recovery Source
To Internal
RESET
P20-P26,
P30-P33
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