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參數資料
| 型號： | Z86U18 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | USB Device Controller(鍵盤及其它外設的理想的USB微控制器) |
| 中文描述： | USB設備控制器（鍵盤及其它外設的理想的的USB微控制器） |
| 文件頁數： | 23/31頁 |
| 文件大小： | 311K |
| 代理商： | Z86U18 |
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Z86E18/U18
Zilog
1.5 MBPS USB Device Controller for Keyboards and HID-Class Peripherals
DS97KEY2301
P R E L I M I N A R Y
23
1
Figure 32. Endpoint 0 CS Register
D7
D6
D5
D4
D3
D2
D1
D0
Out _pkt _rdy
In _pkt _rdy
Force Stall
Data End
Setup End
Send Stall
Serviced Out Packet Ready
Serviced Setup End
001h
Bit No
7
6
Bit Description
Serviced Setup End
Serviced Outpacket
Ready
Send STALL
uc
W
W
SIE
R
R
Description
The microcontroller writes a 1 to this register to clear setup end bit.
The microcontroller writes a 1 to this register to clear out packet ready
bit.
If the microcontroller decodes an invalid descriptor, it writes a 1 to this
register before clearing out_pkt_rdy bit or when microcontroller decodes
a set feature or clear feature USB command from the host.
If the function receives a new setup transaction before the previous one
is complete (entire length of data is transferred), this bit is set. Upon
seeing this bit set, the microcontroller should abort the current set
operation.
R/W R/W During the data phase of a control transfer after the microcontroller has
received/sent the last data as specified in the setup phase, it sets this
bit.
R
W
The SIE writes to this register, when it encounters a protocol violation,
and issues a STALL handshake to the current control transfer.
R/W R/W During the data phase, after the microcontroller has filled the data, it sets
this bit. It is cleared by SIE upon successful transmission of data.
R
W
The SIE sets this bit after writing data to the FIFO. The microcontroller
clears this bit by writing it to Serviced Out Packet Ready bit.
5
W
R
4
Setup End
R
W
3
Data End
2
Sent STALL
1
In Packet Ready
0
Out Packet Ready
Figure 33. Endpoint 0 Write Count Register
D7
D6
D5
D4
D3
D2
D1
D0
Write Count
0000
002h
Bit
3:0
uc
R
SIE
W
Description
The contents indicates the number of bytes in the FIFO.
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