參數(shù)資料
型號(hào)： Z86U18
廠商： ZiLOG, Inc.
英文描述： USB Device Controller(鍵盤(pán)及其它外設(shè)的理想的USB微控制器)
中文描述： USB設(shè)備控制器（鍵盤(pán)及其它外設(shè)的理想的的USB微控制器）
文件頁(yè)數(shù)： 27/31頁(yè)
文件大?。?/td> 311K
代理商： Z86U18
Z86E18/U18
Zilog
1.5 MBPS USB Device Controller for Keyboards and HID-Class Peripherals
DS97KEY2301
P R E L I M I N A R Y
27
1
PROGRAMMING THE Z86E18
Signals Required for E18 EPROM
The TEST pin will be used as a high voltage pin. The high
voltage from this pin will be used to program the EPROM.
It must also be at high voltage in order for any EPROM op-
eration to be done. When this pin is at high voltage, then
an internal signal V
pph
is generated from the high voltage
detect circuitry and the signal being active will be used to
multiplex the remaining pins that are required in all the
EPROM operations.
TEST (Vpp)
This pin is designated a high voltage pin on the Z86E18.
All EPROM operations will require a high voltage on this
pin. The V
pp
supplies the high voltage for the programming
of the EPROM.
Note
: The pins listed below are based on the condition that
the V
pp
is in high voltage.
Mode Latch
The Z86E18 utilizes this pin when high will be used to latch
the mode. This condition will only happen when the V
pph
is
active.
OE (Output Enable)
This regular pin controls the direction of the data bus. The
signal generated goes into the EPROM as the precharge
signal.
When this signal is low, the data is output from the
EPROM. When the signal is high, data is input to the
EPROM.
When the signal is high, the EPROM is precharged. When
the signal is low, the EPROM is evaluated.
EPMH
This regular pin is used to read the option bits when the
EPROM is protected.
When the signal is high, during POR, the option bits can be
read from the EPROM.
Volt_Clamp
This regular pin used the signal to disable the voltage
clamp circuit.
When the signal is low, the voltage clamp circuit is en-
abled. When the signal is high, the voltage clamp circuit is
disabled and margin testing can be done.
CE
This regular pin on the Z86E18 is the chip enable signal for
the EPROM. This signal will be input to the EPROM when
Vpph is high. This signal is an active low signal.
PGM (PGMb—Program Mode)
This regular pin on the Z86E18 allows the EPROM to be
programmed when the signal is logic low, and when the
signal V
pph
is high. The data on the database will be pro-
grammed into the location that is addressed by the internal
counter that generates the address for the EPROM.
ADR CLK (epadr_clk) & ADR CLR (epadr_rst)
The address is generated by an internal address counter
which is clocked through the signal epadr_clk. Each clock
increments the counter by one. The counter can be reset
to zero by the epadr_rst signal. Both epadr_clk and
epadr_rst are external signals.
The epadr_rst signal is an active high signal.
Data to the EPROM
The data to the EPROM are multiplexed with the pins (Da-
ta <7.0>).
Option Bit Programming
In order to program the option bits, the Mode 3 should be
used. Please note the following:
I
The V
pp
pin is set to high voltage (device pin TEST is
driven to high voltage).
I
The ADR CLR signal is driven high for one cycle to reset
the address counter.
I
Three clocks are provided on the ADR CLK pin, which
will advance the counter to the count of 3.
I
The Mode Latch signal is driven high for one cycle to
latch in the data into the Mode Register.
I
The address counter is again reset and the required
data is programmed into location 0, which will program
the 8 locations of the option bits. In the Z86E18, bits 0, 1
and 2 will be used as there are only 3 option bits for this
device.
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