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| 型號： | Z8S18006FSC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 10/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006FSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-10
P R E L I M I N A R Y
DS971800401
PIN DESCRIPTIONS
A0-A19.
A19 form a 20-bit address bus. The Address Bus provides
the address for memory data bus exchanges, up to 1 MB,
and I/O data bus exchanges, up to 64K. The address bus
enters a high-impedance state during reset and external
bus acknowledge cycles. Address line A18 is multiplexed
with the output of PRT channel 1 (T
dress output on reset) and address line A19 is not avail-
able in DIP versions of the Z80180.
Address Bus (Output, active High, tri-state). A0-
OUT
, selected as ad-
BUSACK.
/BUSACK indicated the requesting device, the MPU ad-
dress and data bus, and some control signals, have en-
tered their high-impedance state.
Bus Acknowledge (Output, active Low).
/BUSREQ.
used by external devices (such as DMA controllers) to re-
quest access to the system bus. This request has a higher
priority than /NMI and is always recognized at the end of
the current machine cycle. This signal will stop the CPU
from executing further instructions and places address and
data buses, and other control signals, into the high-imped-
ance state.
Bus Request (Input, active Low). This input is
CKA0, CKA1.
active High). When in output mode, these pins are the
transmit and receive clock outputs from the ASCI baud
rate generators. When in input mode, these pins serve as
the external clock inputs for the ASCI baud rate genera-
tors. CKA0 is multiplexed with /DREQ0, and CKA1 is mul-
tiplexed with /TEND0.
Asynchronous Clock 0 and 1 (Bidirectional,
CKS.
clock for the CSIO channel.
Serial Clock (Bidirectional, active High). This line is
PHI CLOCK.
put is used as a reference clock for the MPU and the ex-
ternal system. The frequency of this output is equal to one-
half that of the crystal or input clock frequency.
System Clock (Output, active High). The out-
/CTS0 - /CTS1.
These lines are modem control signals for the ASCI chan-
nels. /CTS1 is multiplexed with RXS.
Clear to send 0 and 1 (Inputs, active Low).
D0 - D7.
Data Bus = (Bidirectional, active High, tri-state).
D0 - D7 constitute an 8-bit bi-directional data bus, used for
the transfer of information to and from I/O and memory de-
vices. The data bus enters the high-impedance state dur-
ing reset and external bus acknowledge cycles.
DCD0.
Data Carrier Detect 0 (Input, active Low). This is a
programmable modem control signal for ASCI channel 0.
/DREQ0, /DREQ1.
DMA Request 0 and 1 (Input, active
Low). /DREQ is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
for a read or write operation. These inputs can be pro-
grammed to be either level or edge sensed. /DREQ0 is
multiplexed with CKA0.
E.
Enable Clock (Output, active High). Synchronous ma-
chine cycle clock output during bus transactions.
EXTAL.
External Clock Crystal (Input, active High). Crys-
tal oscillator connections. An external clock can be input to
the Z80180/Z8S180/Z8L180 on this pin when a crystal is
not used. This input is Schmitt triggered.
/HALT.
Halt/SLEEP (Output, active Low). This output is
asserted after the CPU has executed either the HALT or
SLP instruction, and is waiting for either non-maskable or
maskable interrupt before operation can resume. It is also
used with the /M1 and ST signals to decode status of the
CPU machine cycle.
/INT0.
Maskable Interrupt Request 0 (Input, active Low).
This signal is generated by external I/O devices. The CPU
will honor these requests at the end of the current instruc-
tion cycle as long as the /NMI and /BUSREQ signals are
inactive. The CPU acknowledges this interrupt request
with an interrupt acknowledge cycle. During this cycle,
both the /M1 and /IORQ signals will become active.
/INT1, /INT2.
Maskable Interrupt Request 1 and 2 (Inputs,
active Low). This signal is generated by external I/O devic-
es. The CPU will honor these requests at the end of the
current instruction cycle as long as the /NMI, /BUSREQ,
and /INT0 signals are inactive. The CPU will acknowledge
these requests with an interrupt acknowledge cycle. Unlike
the acknowledgment for /INT0, during this cycle neither
the /M1 or /IORQ signals will become active.
/IORQ.
IO Request (Output, active Low, tri-state). /ORQ
indicates that the address bus contains a valid I/O address
for an I/O read or I/O write operation. /IORQ is also gener-
ated, along with /M1, during the acknowledgment of the
/INT0 input signal to indicate that an interrupt response
vector can be place onto the data bus. This signal is anal-
ogous to the /IOE signal of the Z64180.
/M1.
Machine Cycle 1 (Output, active Low). Together with
/MREQ, /M1 indicates that the current cycle is the Opcode
fetch cycle of and instruction execution. Together with
/IORQ, /M1 indicates that the current cycle is for an inter-
rupt acknowledge. It is also used with the /HALT and ST
signal to decode status of the CPU machine cycle. This
signal is analogous to the /LIR signal of the Z64180.
/MREQ.
Memory Request (Output, active Low, tri-state).
/MREQ indicates that the address bus holds a valid ad-
dress for a memory read or memory write operation. This
signal is analogous to the /ME signal of Z64180.
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