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| 型號： | Z8S18006FSC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 41/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006FSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-41
1
is used as a clock input, and is divided by 1, 16, or 64 de-
pending on the DR bit and the X1 bit in the ASEXT register.
If these bits are not 111 and the BRG mode bit is ASEXT
is 0, then these bits specify a power-of-two divider for the
PHI clock as shown in Table 9.
Setting or leaving these bits as 111 makes sense for a
channel only when its CKA pin is selected for the CKA
function. CKAO/CKS has the CKAO function when bit 4 of
the System Configuration Register is 0. DCD0/CKA1 has
the CKA1 function when bit 0 of the Interrupt Edge register
is 1.
ASCI STATUS REGISTER 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI
communication, error and modem control signal status,
and enabling or disabling of ASCI interrupts.
RDRF: Receive Data Register Full (bit 7).
RDRF is set to
1 when an incoming data byte is loaded into an empty Rx
FIFO. Note that if a framing or parity error occurs, RDRF is
still set and the receive data (which generated the error) is
still loaded into the FIFO. RDRF is cleared to 0 by reading
RDR and last character in the FIFO from IOSTOP mode,
during RESET and for ASCI0 if the /DCD0 input is auto-en-
abled and is negated (High).
OVRN: Overrun Error (bit 6).
An overrun condition oc-
curs if the receiver has finished assembling a character but
the Rx FIFO is full so there is no room for the character.
However, this status bit is not set until the last character re-
ceived before the overrun becomes the oldest byte in the
FIFO. This bit is cleared when software writes a 1 to the
EFR bit in the CNTLA register, and also by Reset, in
IOSTOP mode, and for ASCI0 if the /DCD0 pin is auto en-
abled and is negated (High).
Note that when an overrun occurs, the receiver does not
place the character in the shift register into the FIFO, nor
any subsequent characters, until the last good character
has come to the top of the FIFO so that OVRN is set, and
software then writes a 1 to EFR to clear it.
Table 6. Divide Ratio
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Divide Ratio
÷
1
÷
2
÷
4
÷
8
÷
16
÷
32
÷
64
External Clock
Figure 35. ASCI Status Registers
Bit
RDRF
OVRN
R
R
R/W
PE
7
6
5
4
3
2
1
0
FE
RE
DCD
0
TDRE
TIE
R
R
ASCI Status Register 0 (STAT0: I/O Address = 04H)
R
R
R/W
Bit
RDRF
OVRN
R
R/W
PE
7
6
5
4
3
2
1
0
FE
RE
TDRE
TIE
R
R
ASCI Status Register 1 (STAT1: I/O Address = 05H)
R
R
R/W
CTSIE
R/W
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| Z8S18006PEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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| Z8S18006VSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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