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參數(shù)資料
| 型號： | Z8S18006FSC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| 中文描述： | 強化Z180微處理器 |
| 文件頁數(shù)： | 45/70頁 |
| 文件大小： | 387K |
| 代理商： | Z8S18006FSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-45
1
Timer Reload Register 0L
RLDR0L
0E H
Timer Reload Register 0H
RLDR0H
0F H
TIMER CONTROL REGISTER (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status.
It also controls enabling and disabling of down counting
and interrupts along with controlling output pin A18/TOUT
for PRT1.
TIF1: Timer Interrupt Flag 1 (bit 7).
When TMDR1 decre-
ments to 0, TIF1 is set to 1. This generates an interrupt re-
quest if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR
is read and the higher or lower byte of TMDR1 is read. Dur-
ing RESET, TIF1 is cleared to 0.
TIF0: Timer Interrupt Flag 0 (bit 6).
When TMDR0 decre-
ments to 0, TIF0 is set to 1. This generates an interrupt re-
quest if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR
is read and the higher or lower byte of TMDR0 is read. Dur-
ing RESET, TIF0 is cleared to 0.
TIE1: Timer Interrupt Enable 1 (bit 5).
When TIE0 is set
to 1, TIF1 = 1 generates a CPU interrupt request. When
TIE0 is reset to 0, the interrupt request is inhibited. During
RESET, TIE0 is cleared to 0.
TOC1, 0: Timer Output Control (bits 3, 2).
TOC1 and
TOC0 control the output of PRT1 using the multiplexed
TOUT/DREQ pin as shown in Table 11. During RESET,
TOC1 and TOC0 are cleared to 0. If bit 3 of the IAR1B reg-
ister is 1, the TOUT function is selected. By programming
TOC1 and TOC0, the TOUT/DREQ pin can be forced
High, Low, or toggled when TMDR1 decrements to 0.
Figure 44. Timer Reload Register Low
Timer Reload Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 45. Timer Reload Register Channel
Timer Reload Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 46. Timer Control Register (TCR: I/O Address = 10H)
Bit
TIF1
TIF0
R/W
R/W
R/W
TIE1
7
6
5
4
3
2
1
0
TIE0
TOC0
TDE1
TDE0
R
R
R/W
R/W
R/W
TOC1
Table 8. Timer Output Control
TOC1 TOC0
0
Output
0
Inhibited
The TOUT/DREQ pin is not
affected by the PRT.
If bit 3 of IAR1B is 1, the
TOUT/DREQ pin is toggles or
set Low or High as indicated.
0
1
1
1
0
1
Toggled
0
1
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