參數(shù)資料
型號(hào)： ZL30402/QCG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 18/44頁(yè)
文件大小： 472K
代理商： ZL30402/QCG1
ZL30402
Data Sheet
25
Zarlink Semiconductor Inc.
Address: 14 H
Address: 19 H
Bit
Name
Functional Description
Default
7-5
RSV
Reserved.
000
4
F8odis
F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns
active high framing pulse output.
0
3
F0odis
F0o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 244 ns
active low framing pulse output.
0
2
F16odis
F16o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 61 ns
active low framing pulse output.
0
1C6dis
6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz clock
output.
0
C19dis
19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz clock
output.
0
Table 13 - Clock Disable Register 2 (R/W)
Bit
Name
Functional Description
Default
7-3
RSV
Reserved.
00000
2MHR
Manual Holdover Release. A change form 0 to 1 on the MHR bit will release the Core
PLL from Auto Holdover to Normal when automatic return from Holdover is disabled
(AHRD is set to 1). This bit is level sensitive and it must be cleared immediately after it
is set to 1 (next write operation). This bit has no effect if AHRD is set to 0.
0
1
AHRD
Automatic Holdover Return Disable. When set high, this bit inhibits the Core PLL
from automatically switching back to Normal mode from Auto Holdover state when the
active Acquisition PLL regains lock to input reference. The active Acquisition PLL is the
Acquisition PLL to which the Core PLL is currently connected.
0
0RSV
Reserved.
0
Table 14 - Core PLL Control Register (R/W)
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