參數(shù)資料
型號(hào)： ZL30402/QCG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 472K
代理商： ZL30402/QCG1
ZL30402
Data Sheet
28
Zarlink Semiconductor Inc.
Address: 43 H
5.0
Applications
This section contains application specific details for Mode Switching and Master Clock Oscillator calibration.
5.1
ZL30402 Mode Switching - Examples
The ZL30402 is designed to transition from one mode to the other driven by the internal State Machine or by
manual control. The following examples present a couple of typical scenarios of how the ZL30402 can be employed
in network synchronization equipment (e.g., timing modules, line cards or stand alone synchronizers).
5.1.1
System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL
The FREE-RUN to HOLDOVER to NORMAL transition represents a sequence of steps that will most likely occur
during a new system installation or scheduled maintenance of timing cards. The process starts from the RESET
state and then transitions to Free-run mode where the system (card) is being initialized. At the end of this process
the ZL30402 should be switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the
reference clock is available, the ZL30402 will transition briefly into Holdover to acquire synchronization and switch
automatically to Normal mode. If the reference clock is not available at this time, as it may happen during new
system installation, then the ZL30402 will stay in Holdover indefinitely. While in Holdover mode, the Core PLL will
continue generating clocks with the same accuracy as in the Free-run mode, waiting for a good reference clock.
When the system is connected to the network (or timing card switched to a valid reference) the Acquisition PLL will
quickly synchronize and clear its own Holdover status (PAH bit). This will enable the Core PLL to start the
synchronization process. After acquiring lock, the ZL30402 will automatically switch from Holdover into Normal
mode without system intervention. This transition to the Normal mode will be flagged by the LOCK status bit and
pin.
Figure 7 - Transition from Free-Run to Normal Mode
Bit
Name
Functional Description
Default
7-0
MCFC7 - 0
Master Clock Frequency Calibration. This byte contains bit 7 to
bit 0 of the Master Clock Frequency Calibration Register.
00000
000
Table 21 - Master Clock Frequency Calibration Register 1 (R/W)
NORMAL
(LOCKED)
00
AUTO
HOLD-
OVER
HOLD-
OVER
01
FREE-
RUN
10
RESET
Ref: OK &
MS2, MS1 == 00
{AUTO}
Ref: OK --> FAIL &
MS2, MS1 == 00
{AUTO}
MS2, MS1 == 01 OR
RefSel change
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=1 &
MHR= 0 -->1 then 1-->0
{MANUAL}
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=0
{AUTO}
MS2, MS1 == 10 forces
unconditional return from
any state to Free-run
MS2, MS1! = 10
RESET == 1
RefSel Change
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