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參數(shù)資料
| 型號： | ZL30402/QCG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 44/44頁 |
| 文件大小： | 472K |
| 代理商： | ZL30402/QCG1 |
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ZL30402
Data Sheet
9
Zarlink Semiconductor Inc.
35
Tms
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
36
Tclk
IEEE1149.1a Test Clock Signal (5.5 V tolerant input). Input clock for the
JTAG test logic. If not used, this pin should be pulled up to VDD.
37
Trst
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG
TAP controller. This pin should be pulsed low on power-up to ensure that the
device in the normal functional state. This pin is internally pulled up to VDD. If
not used, this pin should be connected to GND.
38
Tdi
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test
instructions and data. This pin is internally pulled up to VDD. If not used, this
pin should be left unconnected.
39
NC
No internal bonding Connection. Leave unconnected.
40
NC
No internal bonding Connection. Leave unconnected.
41
IC
Internal Connection. Leave unconnected.
42
C1.5o
Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz
DS1 rate clock.
43
C6o
Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz
DS2 rate clock.
44
IC
Internal Connection. Connect this pin to Ground.
45
GND
Ground.
46
C19o
Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz
clock.
47
RefSel
Reference Source Select (Input). A logic low selects the PRI (primary)
reference source as the input reference signal and logic high selects the SEC
(secondary) input. The logic level at this input is sampled at the rising edge of
F8o. This pin is internally pulled down to GND.
48
RefAlign
Reference Align (Input). In Hardware Control a high to low transition at this
input initiates phase realignment between the input reference and the
generated output clocks. This pin is internally pulled down to GND.
49
VDD
Positive Power Supply.
50
NC
No internal bonding Connection. Leave unconnected.
51
C20i
Clock 20 MHz (5.5 V tolerant input). This pin is the input for the 20 MHz
Master Clock Oscillator.
52
GND
Digital Ground.
Pin Description (continued)
Pin #
Name
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30406 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGC | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK MLTPLR SGL UP TO 19.44MHZ 64TQFP - Trays |
| ZL30406QGC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGG1 | 制造商:Microsemi Corporation 功能描述:IC PB FREE T1/E1 SYS. SYNC+STRATUM 3 H/O 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH CLOCK MULTIPLIER PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP |
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