參數(shù)資料
型號: ZL38001
廠商: Zarlink Semiconductor Inc.
英文描述: Low-Voltage Acoustic Echo Canceller with Low ERL Compensation
中文描述: 低電壓聲回波抵消低廣深港高速補償
文件頁數(shù): 25/47頁
文件大小: 668K
代理商: ZL38001
ZL38001
Data Sheet
25
Zarlink Semiconductor Inc.
Timing is over recommended temperature range and recommended power supply voltages.
Figure 10 - Master Clock - MCLK
AC Electrical Characteristics
- Microport Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Notes
1
Input Data Setup
t
IDS
30
ns
2
Input Data Hold
t
IDH
30
ns
3
Output Data Delay
t
ODD
100
ns
C
L
= 150 pF
4
Serial Clock Period
t
SCP
500
ns
5
SCLK Pulse Width High
t
SCH
250
ns
6
SCLK Pulse Width Low
t
SCL
250
ns
7
CS Setup-Intel
t
CSSI
200
ns
8
CS Setup-Motorola
t
CSSM
100
ns
9
CS Hold
t
CSH
100
ns
10
CS to Output High Impedance
t
OHZ
100
ns
C
L
= 150 pF
Characteristic
Symbol
CMOS Level
Units
CMOS reference level
V
CT
0.5*V
DD
V
Input HIGH level
V
H
0.9*V
DD
V
Input LOW level
V
L
0.1*V
DD
V
Rise/Fall HIGH measurement point
V
HM
0.7*V
DD
V
Rise/Fall LOW measurement point
V
LM
0.3*V
DD
V
Table 6 - Reference Level Definition for Timing Measurements
MCLK
(I)
V
H
V
L
V
CT
T=1/f
CLK
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
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