參數(shù)資料
型號： ZL38002DGB1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述： DATACOM, ISDN ECHO CANCELLER, PDSO36
封裝： 0.300 INCH, LEAD FREE, QSOP-36
文件頁數(shù)： 10/47頁
文件大小： 440K
代理商： ZL38002DGB1
ZL38002
Data Sheet
10
Zarlink Semiconductor Inc.
2.0 PCM Data I/O
The PCM data transfer for the ZL38002 is provided through two PCM ports. One port consists of Rin and Sout pins
while the second port consists of Sin and Rout pins. The data are transferred through these ports according to
either ST-BUS, GCI or SSI conventions detected automatically by the device. The ZL38002 determines the
convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied
to the F0i pin, the ZL38002 will assume ST-BUS operation. When a valid GCI (active high) frame pulse is applied to
the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device is set to SSI
operation. Figures 3 to 6 show timing diagrams of these 3 PCM-interface operation conventions.
2.1 ST-BUS and GCI Operation
The ST-BUS PCM interface conforms to Zarlink’s ST-BUS standard with an active-low frame pulse. Input data is
clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bit cell and output data bit
boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface
corresponds to the GCI standard commonly used in Europe with an active-high frame pulse. Input data is clocked in
by the falling edge of the bit clock (C4i) three-quarters of the way into the bit cell and output data bit boundaries
(Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.)
Either of these interfaces (ST-BUS or GCI) can be used to transport 8 bit companded PCM data (using one
timeslot) or 16 bit 2’s complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on
the Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 2. Figures 3 to 6
illustrate the timeslot allocation for each of these four modes.
Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)
C4i
F0i (ST-BUS)
Sin
Rout
Rin
Sout
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
outputs = High impedance
inputs = don’t care
In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1
and PORT2 into different modes.
PORT1
PORT2
0
B
1
2
3
4
F0i (GCI)
start of frame (stbus & GCI)
EC
EC
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相關代理商/技術參數(shù)
參數(shù)描述
ZL38002DGE1 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 36QSOP /B - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCELLER AEC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCELLER AEC 36SSOP
ZL38002DGF1 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 36QSOP /B - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCELLER AEC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCELLER AEC 36SSOP
ZL38002QDG 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 48TQFP - Trays
ZL38002QDG1 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 48TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ECHO CANCELLER CHIP 1CH G.711 W/OUT TONE DETECTION 48TQFP - Trays
ZL38003 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication
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