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參數資料
| 型號： | ZL38002DGB1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller With Noise Reduction |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PDSO36 |
| 封裝： | 0.300 INCH, LEAD FREE, QSOP-36 |
| 文件頁數： | 33/47頁 |
| 文件大?。?/td> | 440K |
| 代理商： | ZL38002DGB1 |
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ZL38002
Data Sheet
33
Zarlink Semiconductor Inc.
Figure 10 - Automatic Rout Gain Reduction (RoutGR)
Register Table 20 - NLP Threshold Register
Bit
Name
Description
0
RoutGR
This bit will provide an automatic signal reduction on Rout by 12 db when
double talk is present with this bit set to 1.
Bit
Name
Description
15-0
NLPTH15-
NLPTH0
This register allows the user to program the level of the Non-Linear
Processor Threshold. The 16 bit 2’s complement linear value
defaults
to
1AAh. The maximum value is 7FFFh = 0.9999. Higher value corresponds
to higher threshold. The high byte is in Register 2 and the low byte is in
Register 1.
Read/Write Page 0, Address: 32
H
Reset Value: 2A
H
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RoutGR
Read/Write Page 01, Address: 35
H
Reset Value: 01
H
15
14
13
12
11
10
9
8
NLPTH15
NLPTH14
NLPTH13
NLPTH12
NLPTH11
NLPTH10
NLPTH9
NLPTH8
Read/Write Page AA, Address: 34
H
Reset Value: AA
H
7
6
5
4
3
2
1
0
NLPTH7
NLPTH6
NLPTH15
NLPTH4
NLPTH3
NLPTH2
-NLPTH1
NLPTH0
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