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參數(shù)資料
| 型號： | ZL38002DGB1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller With Noise Reduction |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PDSO36 |
| 封裝： | 0.300 INCH, LEAD FREE, QSOP-36 |
| 文件頁數(shù)： | 35/47頁 |
| 文件大?。?/td> | 440K |
| 代理商： | ZL38002DGB1 |
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ZL38002
Data Sheet
35
Zarlink Semiconductor Inc.
Register Table 23 - Receive (Rout) Peak Detect Registers (RPDR1) & (RPDR2)
Bit
Name
Description
15-0
ROPD15-
ROPD0
These peak detector registers allow the user to monitor the receive out
signal (Rout) peak signal level at reference point R1 (see Figure 1). The
information is in 16-bit 2’s complement linear coded format presented in
two 8 bit registers. The high byte is in Register 2 and the low byte is in
Register 1.
Bit
Name
Description
15-0
A_AS15-0
Actual mu sent to acoustic LMS. This register is where we can feed
externally calculated mu value. This register allows the user to program
control the adaptation speed. The default value is 1000h corresponding to
decimal value of 2.0. The high byte is in Register 2 and the low byte is in
Register 1. Smaller values correspond to slower adaptation speed.
Register Table 24 - Adaptation Speed Registers (ASR1) & (ASR2)
Read/Write Page 0, Address: 3B
H
Reset Value: 00
H
15
14
13
12
11
10
9
8
ROPD
15
ROPD
14
ROPD
13
ROPD
12
ROPD
11
ROPD
10
ROPD
9
ROPD
8
Read/Write Page 0, Address: 3A
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
ROPD
7
ROPD
6
ROPD
15
ROPD
4
ROPD
3
ROPD
2
ROPD
1
ROPD
0
Read/Write Page 0, Address: 3D
H
Reset Value: 10
H
15
14
13
12
11
10
9
8
A_AS15
A_AS14
A_AS13
A_AS12
A_AS11
A_AS10
A_AS9
A_AS8
Read/Write Page 0, Address: 3C
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
A_AS7
A_AS6
A_AS5
A_AS4
A_AS3
A_AS2
A_AS1
A_AS0
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| ZL38003 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
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