參數(shù)資料
型號: ZL38065GDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: 32 Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 13/48頁
文件大?。?/td> 658K
代理商: ZL38065GDG
ZL38065
Data Sheet
13
Zarlink Semiconductor Inc.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
The Advanced NLP uses an exponential noise ramping scheme to quickly and more accurately estimate the
background noise level. A linear noise ramping method can also be used. The InjCtrl bit in Control Register 3
selects the ramping scheme.
The NLINC register is used to set the ramping speed. When InjCtrl = 1, a lower value will give faster ramping. The
Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will scale
the injected noise level down, conversely, raising the value will scale the comfort noise up.
IMPORTANT NOTE: The Noise Scaling register has been pre-programmed with G.168 compliant values. Changing
this value may result in undesirable comfort noise performance and G.168 test failures.
The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for
background noise. These features can be disabled by setting the NLRun1 and NLRun2 bits in Control Register 3 to
“0”.
1.5 Disable Tone Detector
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (
±
21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (±25 degrees) every
450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the
Tone Detector will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
The ZL38065 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 6 and to the
Interrupts
section.
Figure 6 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e., IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.
TD bit
Rin
Sin
Echo Canceller A
Tone
Detector
Tone
Detector
Status reg
ECA
TD
bit
Rin
Sin
Echo Canceller B
Tone
Detector
Tone
Detector
Status reg
ECB
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