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參數(shù)資料
| 型號： | ZL38065GDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 32 Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 658K |
| 代理商： | ZL38065GDG |
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ZL38065
Data Sheet
21
Zarlink Semiconductor Inc.
6.4 Power Up Sequence
On power up, the RESET pin must be held low for 100
μ
s. Forcing the RESET pin low will put the ZL38065 in
power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated.
The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500
μ
s for the PLL to
lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers
reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware
reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least
500 ns and no more than 1500 ns before being released. A software reset is accomplished by programming a “1” to
each of the PWUP bits in the Main Control Registers, waiting 250
μ
s (2 frames) and then programming a “0” to
each of the PWUP bits.
The user must then wait 500
μ
s for the PLL to relock. Once the PLL has locked, the user can power up the 16
groups of echo cancellers individually by writing a “1” into the PWUP bit in Main Control Register of each echo
canceller group.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00
hex
to Base Address+3F
hex
,
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00
hex
to Base Address+3F
hex
, for the specific application.
Figure 12 - Power Up Sequence Flow Diagram
System Powerup
Reset Held Low
Delay 100
μ
s
Reset High
MCLK Active
Delay 500
μ
s
Reg. Reset
Software
Hardware
Reset Low
Delay 1000 ns
Reset High
PWUP to “1”
Delay 250
μ
s
PWUP to “0”
Delay 500
μ
s
ECAN Ready
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL38065GDG2 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.164/G.165/G.168/G.711 W/ TONE DET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 208LBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCEL 208LBGA |
| ZL38065QCG | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.164/G.165/G.168/G.711 W/ TONE DET - Trays |
| ZL38065QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 32CH VEC+ENHANCED NOISE MATCHING 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.164/G.165/G.168/G.711 W/ TONE DET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 100LQFP 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCEL 100LQFP |
| ZL38070 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:256 Channel Voice Echo Canceller |
| ZL38070_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:256 Channel Voice Echo Canceller |
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