參數(shù)資料
型號(hào): ZL38065GDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: 32 Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 32/48頁
文件大?。?/td> 658K
代理商: ZL38065GDG
ZL38065
Data Sheet
32
Zarlink Semiconductor Inc.
Power-up
40
hex
ECA: Gains Register 2
Page 0
A12=0
A11=0
R/W Address:
1D
hex
+ Base Address
R/W Address:
3D
hex
+ Base Address
Bit 1
Rout1
ECB: Gains Register 2
Bit 7
0
Bit 6
Rin2
Bit 5
Rin1
Bit 4
Rin0
Bit 3
0
Bit 2
Rout2
Bit 0
Rout0
Power-up
00
hex
ECA: Gains Register1
Page 0
A12=0
A11=0
R/W Address:
1C
hex
+ Base Address
R/W Address:
3C
hex
+ Base Address
Bit 1
Sout1
ECB: Gains Register 1
Bit 5
Sin1
Functional Description of Register Bits
Bit 7
0
Bit 6
Sin2
Bit 4
Sin0
Bit 3
0
Bit 2
Sout2
Bit 0
Sout0
This register is used to select gain values on RIN, ROUT, SIN and SOUT.
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above),
and has three gain bits. The following table indicates how these gain bits are used:
Bit2 Bit1 Bit0 Gain Level
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1 -3 dB
0 1 0 -6 dB
0 0 1 -9 dB
0 0 0 -12 dB
+9 dB
+6 dB)
+3 dB
0 dB (default)
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and
will override the settings in Gains.
Power-up
08
hex
ECA: NLP Threshold 2 (NLPTHR2)
Page 0
A12=0
A11=0
R/W Address:
1E
hex
+ Base Address
R/W Address:
3E
hex
+ Base Address
Bit 1
NLPTH1
ECB: NLP Threshold 2 (NLPTHR2)
Bit 7
NLPTH7
Bit 6
NLPTH6
Bit 5
NLPTH5
Bit 4
NLPTH4
Bit 3
NLPTH3
Bit 2
NLPTH2
Bit 0
NLPTH0
Functional Description of Register Bits
This register is used to force the NLP off when very small signals exist on RIN. NLP is forced off if RIN is
below NLPTHR2 << 4. Raising this value can help prevent NLP masking at very low signal levels.
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