參數(shù)資料
型號(hào): ZL50015QCC1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BJC, LQFP-256
文件頁數(shù): 91/122頁
文件大?。?/td> 926K
代理商: ZL50015QCC1
ZL50015
Data Sheet
91
Zarlink Semiconductor Inc.
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler
oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal
accuracy only affects the output clock accuracy in the freerun or the holdover mode. The crystal specification is as
follows:
25.1.2 External Clock Oscillator
When an external clock oscillator is used, numerous parameters must be considered. They include absolute
frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo
output should be left open as shown in Figure 24 on page 91. XC is a buffered version of the 20 MHz input clock
connected to the internal circuitry.
Figure 24 - Clock Oscillator Circuit
For applications requiring
±
32 ppm clock accuracy, the following requirements should be met.
Frequency
20 MHz
Tolerance
As required
Oscillation Mode
Fundamental
Resonance Mode
Parallel
Load Capacitance
20 pF - 32 pF
Maximum Series Resistance
35
Approximate Drive Level
1 mW
Frequency
20.000 MHz
Tolerance
±
32 ppm
Rise and Fall Time
10 ns
Duty Cycle
40% to 60%
+3.3V
20 MHz OUT
GND
0.1 uF
+3.3 V
OSCo
OSCi
No Connection
XC
1K DX
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