參數(shù)資料
型號(hào)： ZL50019
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述： 2度增強(qiáng)數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 30/115頁
文件大小： 866K
代理商： ZL50019
ZL50019
Data Sheet
30
Zarlink Semiconductor Inc.
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
Figure 15 - Input Bit Delay and Factional Sampling Point
8.3 Output Advancement Programming
This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 31 (SOCR0 - 31).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 46 on page 77. The output bit
advancement can vary from 0 to 7 bits.
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)
Nominal Channel n+1 Boundary
7
6
5
4
3
2
1
0
7
0
000 01
000 10
000 00
(Default)
000 11
001 01
001 10
001 00
001 11
010 01
010 10
010 00
010 11
011 01
011 10
011 00
011 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset
Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point
Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)
111 00
111 10
111 01
110 11
110 00
110 10
110 01
101 11
101 00
101 10
101 01
100 11
100 00
100 10
100 01
111 11
STi[n]
Nominal Channel n Boundary
FPi
STio[n]
Bit Adv = 0
(Default)
Channel 0
7
Channel 1
6 5 4 3 2 1
0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Channel 2
2 1 0
4
3
Last Channel
STio[n]
Bit Adv = 1
Channel 0
7
Channel 1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
Channel 2
2 1 0
3
Last Channel
Bit Advancement = 1
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
2 1
相關(guān)PDF資料
PDF描述
ZL50019GAC Enhanced 2 K Digital Switch with Stratum 4E DPLL
ZL50019QCC Enhanced 2 K Digital Switch with Stratum 4E DPLL
ZL50022 Enhanced 4 K Digital Switch with Stratum 4E DPLL
ZL50022GAC Enhanced 4 K Digital Switch with Stratum 4E DPLL
ZL50022QCC Enhanced 4 K Digital Switch with Stratum 4E DPLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50019_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL
ZL50019GAC 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION AND S4 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA
ZL50019GAG2 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH RATE CONVERSION+S4E DPLL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA
ZL50019QCC 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION AND S4 - Trays
ZL50019QCG1 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH+CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP
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