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參數(shù)資料
| 型號(hào)： | ZL50019 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | 2度增強(qiáng)數(shù)字交換與地層4E條數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 42/115頁(yè) |
| 文件大?。?/td> | 866K |
| 代理商： | ZL50019 |
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ZL50019
Data Sheet
42
Zarlink Semiconductor Inc.
18.2 Device Initialization on Reset
Upon power up, the ZL50019 should be initialized as follows:
Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high
Set the TRST pin to low to disable the JTAG TAP controller
Reset the device by pulsing the RESET pin to zero for longer than 1
μ
s
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
Wait at least 500
μ
s prior to the next microport access (see Note below)
Use the block programming mode to initialize the connection memory
Note
: If an external oscillator is used, the waiting time is 500
μ
s. Without the external oscillator, if CKi is
16.384 MHz, the waiting time is 500
μ
s; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the
waiting time is 2 ms.
Release the ODE pin from low to high after the connection memory is programmed
18.3 Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There
are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while
SRSTSW (bit 1) resets the rest of the switch.
19.0 Pseudo Random Bit Generation and Error Detection
The ZL50019 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 2
15
-1 pseudorandom code (ITU O.151).
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125
μ
s). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.
For each input stream, there is a set of registers for the BER test. The registers are as follows:
BER Receiver Control Register (
BRCR
) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register
(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
BER Receiver Start Register (
BRSR
) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the
BER sequence will start to be compared.
BER Receiver Length Register (
BRLR
) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence
will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256
channels at the data rates of 2.048, 4.096, 8.192 or 16.384 Mbps, respectively. The minimum length of the
BER test is a single channel. The user must take care to program the correct channel length for the BER test
so that the channel length does not exceed the total number of channels available in the stream.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50019GAC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019QCC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50022 | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
| ZL50022GAC | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
| ZL50022QCC | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50019_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019GAC | 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION AND S4 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50019GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH RATE CONVERSION+S4E DPLL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50019QCC | 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION AND S4 - Trays |
| ZL50019QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH+CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
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