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參數(shù)資料
| 型號： | ZL50023GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 4 K Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA256 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256 |
| 文件頁數(shù)： | 19/80頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | ZL50023GAC |
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ZL50023
Data Sheet
19
Zarlink Semiconductor Inc.
6.0 ST-BUS and GCI-Bus Timing
The ZL50023 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the
device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by
the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge
of CKo while FPo goes high. The data rates define the number of channels that are available in a 125
μ
s frame
pulse period.
By default, the ZL50023 is configured for ST-BUS input and output timing. To set the input timing to conform to the
GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing
to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse
Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the
polarity (positive-going or negative-going) of the output clocks.
7.0 Output Timing Generation
The ZL50023 generates frame pulse and clock timing. There are four output frame pulse pins (FPo0 - 3) and four
output clock pins (CKo0 - 3). All output frame pulses are 8 kHz output signals. By default, the output frame
boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1,
CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. The
duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 4 on
page 19. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode
Selection (IMS) register.
The output timing is dependent on the timing mode that is selected. When the device is in Divided Clock mode, the
frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is 8.192 MHz,
the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output a
4.096 MHz or 8.192 MHz clock signal.
The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50023 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.
The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and
CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing.
Pin Name
Output Timing Rate
Output Timing Unit
FPo0 pulse width
244
ns
CKo0
4.096
MHz
FPo1 pulse width
122
ns
CKo1
8.192
MHz
FPo2 pulse width
61
ns
CKo2
16.384
MHz
FPo3 pulse width
244, 122, 61 or 30
ns
CKo3
4.096, 8.192, 16.384 or 32.768
MHz
Table 4 - Output Timing Generation
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| ZL50030_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
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